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this is information on a product in full production. may 2012 doc id 18340 rev 3 1/104 1 spc56ap60x, spc56ap54x spc560p60x, spc560p54x 32-bit power architecture ? based mcu with 1088 kb flash memory and 80 kb ram for automotive ch assis and safety applications datasheet ? production data features 64 mhz, dual issue, 32-bit cpu core complex (e200z0h) ? compliant with power architecture ? embedded category ? variable length encoding (vle) memory organizazion ? up to 1024 kb on-chip code flash memory with additional 64 kb for eeprom emulation (data flash), with ecc, with erase/program controller ? up to 80 kb on-chip sram with ecc fail safe protection ? ecc protection on system sram and flash ? safety port ? swt with servicing sequence pseudo- random generator ? power management ? non-maskable interrupt for both cores ? fault collection and control unit (fccu) ? safe mode of system-on-chip (soc) ? register protection scheme nexus ? l2+ interface single 3.3 v or 5 v supply for i/os and adc 2 on-platform peripherals set with 2 intc 16-channel edma cont roller with multiple transfer request sources general purpose i/os (80 gpio + 26 gpi on lqfp144; 49 gpio + 16 gpi on lqfp100) 2 general purpose etimer units ? 6 timers, each with up/down count capabilities ? 16-bit resolution, cascadable counters ? quadrature decode with rotation direction flag ? double buffer input capture and output compare communications interfaces ? 2 linflex modules (lin 2.1, 1 master/slave, 1 master only) ? 5 dspi modules with automatic chip select generation ? 2 flexcan interfaces (2.0b active) with 32 message buffers ? 1 safety port based on flexcan; usable as third can when not used as safety port ? 1 flexray? module (v2.1) with dual or single channel, 64 message buffers and up to 10 mbit/s 2 crc units with three contexts and 3 hardwired polynomials(crc8,crc32 and crc-16-ccitt) 10-bit a/d converter ? 27 input channels and pre-sampling feature ? conversion time < 1 s including sampling time at full precision ? programmable cross triggering unit (ctu) ? 4 analog watchdog with interrupt capability on-chip can/uart bootstrap loader with boot assist module (bam) ambient temperature ranges: ?40 to 125 c or ?40 to 105 c table 1. device summary package part number 768 kb flash 1 mb flash lqfp144 spc560p54l5 spc56ap54l5 spc560p60l5 spc56ap60l5 lqfp100 spc560p54l3 spc56ap54l3 SPC560P60L3 spc56ap60l3 lqfp100 14 x 14 mm lqfp144 20 x 20 mm www.st.com
contents spc56xp54x, spc56xp60x 2/104 doc id 18340 rev 3 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5 feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.1 high performance e200z0h core processor . . . . . . . . . . . . . . . . . . . . . . 13 1.5.2 crossbar switch (xbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5.3 enhanced direct memory access (edma) . . . . . . . . . . . . . . . . . . . . . . . 14 1.5.4 on-chip flash memory with ecc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5.5 on-chip sram with ecc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5.6 interrupt controller (intc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5.7 system clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5.8 frequency modulated phase-locked loop (fmpll) . . . . . . . . . . . . . . . . 16 1.5.9 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.10 internal rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.11 periodic interrupt timer (pit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.12 system timer module (stm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.13 software watchdog timer (swt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.14 fault collection and control unit (fccu) . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.15 system integration unit (siul) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.16 boot and censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.5.17 error correction status module (ecsm) . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.18 flexcan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.19 safety port (flexcan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5.20 flexray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.5.21 serial communication interface module (linflex) . . . . . . . . . . . . . . . . . 21 1.5.22 deserial serial peripheral interface (dspi) . . . . . . . . . . . . . . . . . . . . . . 22 1.5.23 etimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.5.24 analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5.25 cross triggering unit (ctu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5.26 cyclic redundancy check (crc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.5.27 nexus development interface (ndi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.5.28 ieee 1149.1 (jtag) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
spc56xp54x, spc56xp60x contents doc id 18340 rev 3 3/104 1.5.29 on-chip voltage regulator (vreg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2 package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 27 2.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.1 power supply and reference voltage pins . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.2 system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2.3 pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.4 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.5.1 general notes for specifications at maximum junction temperature . . . 56 3.6 electromagnetic interference (emi) characte ristics . . . . . . . . . . . . . . . . . 58 3.7 electrostatic discharge (esd) characteristics . . . . . . . . . . . . . . . . . . . . . 58 3.8 power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 58 3.8.1 voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 58 3.8.2 voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 60 3.9 power up/down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.10 nvusro register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.10.1 nvusro[pad3v5v] field description . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.11 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.11.1 dc electrical characteristics (5 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.11.2 dc electrical characteristics (3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.11.3 i/o pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.12 main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.13 fmpll electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.14 16 mhz rc oscillator electrical characterist ics . . . . . . . . . . . . . . . . . . . . 74 3.15 analog-to-digital converter (adc) electrical characteristics . . . . . . . . . . 74 3.15.1 input impedance and adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.15.2 adc conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.16 flash memory electrical char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 81
contents spc56xp54x, spc56xp60x 4/104 doc id 18340 rev 3 3.17 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.17.1 pad ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.18 ac timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.18.1 reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.18.2 ieee 1149.1 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.18.3 nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.18.4 external interrupt timing (irq pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 3.18.5 dspi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.1 ecopack? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.2.1 lqfp144 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.2.2 lqfp100 mechanical outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
spc56xp54x, spc56xp60x list of tables doc id 18340 rev 3 5/104 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. spc56xp54/60 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. spc56xp54/60 device configuration difference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. spc56xp54/60 series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 6. system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 7. pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 8. parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 9. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 10. recommended operating conditions (5.0 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 11. recommended operating conditions (3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 12. thermal characteristics for 144-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 13. thermal characteristics for 100-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 14. emi testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 15. esd ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 16. approved npn ballast components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 17. voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 18. low voltage monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 19. pad3v5v field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 20. dc electrical characteristics (5.0 v, nvusro[pad3v5v]=0) . . . . . . . . . . . . . . . . . . . . . . 64 table 21. supply current (5.0 v, nvusro[pad3v5v]=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 22. dc electrical characteristics (3.3 v, nvusro[pad3v5v]=1) . . . . . . . . . . . . . . . . . . . . . . 67 table 23. supply current (3.3 v, nvusro[pad3v5v]=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 24. peripherals supply current (5 v and 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 25. i/o supply segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 26. i/o consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 27. main oscillator electrical characteristics (5 .0 v, nvusro[pad3v5v]=0) . . . . . . . . . . . . . 72 table 28. main oscillator electrical characteristics (3 .3 v, nvusro[pad3v5v]=1) . . . . . . . . . . . . . 72 table 29. input clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 30. pllmrfm electrical specifications (v ddpll = 1.08 v to 1.32 v, v ss = v sspll = 0 v, ta = tl to th)? . . . . . . . . . . . . . . . . . . . 73 table 31. 16 mhz rc oscillator electrical ch aracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 32. adc conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 33. program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 34. flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 35. flash read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 36. output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 37. reset electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 38. jtag pin ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 39. nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 40. external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 41. dspi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 42. lqfp144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 43. lqfp100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 44. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
list of figures spc56xp54x, spc56xp60x 6/104 doc id 18340 rev 3 list of figures figure 1. spc56xp54/60 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2. lqfp176 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 3. lqfp144 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 4. lqfp100 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 5. power supplies constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 6. independent adc supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 7. power supplies constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 8. independent adc supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 9. voltage regulator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 10. power-up typical sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 11. power-down typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 12. brown-out typical sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 13. i/o input dc electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 14. i/o input dc electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 15. adc characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 16. input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 17. input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 18. transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 19. spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 20. start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 21. noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 22. jtag test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 23. jtag test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 24. jtag boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 25. nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 26. nexus event trigger and test clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 9 figure 27. nexus tdi, tms, tdo timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 28. external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 29. dspi classic spi timing ? master, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 30. dspi classic spi timing ? master, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 31. dspi classic spi timing ? slave, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 32. dspi classic spi timing ? slave, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 33. dspi modified transfer format timing ? master, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 34. dspi modified transfer format timing ? master, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 35. dspi modified transfer format timing ? slave, cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 36. dspi modified transfer format timing ? slave, cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 37. dspi pcs strobe (pcss) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 38. lqfp144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 39. lqfp100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 40. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
spc56xp54x, spc56xp60x introduction doc id 18340 rev 3 7/104 1 introduction 1.1 document overview this document provides electrical specific ations, pin assignments, and package diagrams for the spc56xp54/60 series of microcontroller units (mcus). it also describes the device features and highlights important electrical and physical characteristics. for functional characteristics, refer to the device reference manual. 1.2 description this 32-bit system-on-chip (soc) automotive microcontroller family is the latest achievement in integrated automotive application controllers. it belongs to an expanding range of automotive-focused products designed to addr ess chassis applications specifically the airbag application. this family is one of a series of next-generation integrated automotive microcontrollers based on the power architecture technology. the advanced and cost-efficient host processor core of this automotive controller family complies with the power architecture embedded category. it operates up to 64 mhz and offers high performance processing optimized for low power consumption. it capitalizes on the available development infrastructure of current power architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. 1.3 device comparison ta bl e 2 provides a summary of different members of the spc56xp54/60 family and their features?relative to full-featured version?to enable a comparison among the family members and an understanding of the range of functionality offered within this family. table 2. spc56xp54/60 device comparison feature spc560p54 spc560p60 spc56ap54 spc56ap60 code flash memory (with ecc) 768 kb 1 mb 768 kb 1 mb data flash / ee (with ecc) 64 kb sram (with ecc) 64 kb 80 kb 64 kb 80 kb processor core 32-bit e200z0h 32-bit dual e200z0h instruction set vle cpu performance 0-64 mhz fmpll (frequency-modulated phase- locked loop) modules 1 intc (interrupt controller) channels 148 pit (periodic interrupt timer) 1 (includes four 32-bit timers)
introduction spc56xp54x, spc56xp60x 8/104 doc id 18340 rev 3 spc56xp54/60 is present on the market in two different options enabling different features: full-featured, and airbag configuration. ta b l e 3 shows the main differences between the two versions. enhanced dma (direct memory access) channels 16 flexray yes (64 message buffer) flexcan (controller area network) 3 (1),(2) safety port yes (via third flexcan module) fccu (fault collection and control unit) yes (3) ctu (cross triggering unit) yes etimer channels 2 6 flexpwm (pulse-wid th modulation) channels no analog-to-digital converters (adc) one (10-bit, 27-channel) (4) linflex modules 2 (1 master/slave, 1 master only) dspi (deserial serial peripheral interface) modules 5 (5) crc (cyclic redundancy check) units 2 (6) jtag interface yes nexus port controller (npc) yes (level 2+) (7) supply digital power supply (8) 3.3 v or 5 v single supply with external transistor analog power supply 3.3 v or 5 v internal rc oscillator 16 mhz external crystal oscillator 4?40 mhz packages lqfp100 lqfp144 lqfp100 lqfp144 lqfp176 (9) temperature standard ambient temperature ?40 to 125 c 1. each flexcan module has 32 message buffers. 2. one flexcan module can act as a safety port with a bit rate as high as 7.5 mbit/s. 3. enhanced fccu version 4. same amount of adc channels as on spc560p44/50 not considering the internally connected ones. 26 channels on lqfp144 and 16 channels on lqfp100. 5. increased number of cs for dspi_1 6. upgraded specification with addition of 8-bits po lynomial (crc-8 vda can) support and 3rd context 7. improved debugging capability with data trace capability and incr eased nexus throughput ava ilable on emulation package 8. 3.3 v range and 5 v range correspond to different orderable parts. 9. software development package onl y. not available for production. table 2. spc56xp54/60 device comparison (continued) feature spc560p54 spc560p60 spc56ap54 spc56ap60
spc56xp54x, spc56xp60x introduction doc id 18340 rev 3 9/104 1.4 block diagram figure 1 shows a top-level block diagram of the spc56xp54/60 mcu. ta bl e 4 summarizes the functions of the blocks. table 3. spc56xp54/60 device configuration difference feature full-featured airbag ctu (cross triggering unit) yes no flexray yes (64 message buffer) no dspi (deserial serial peripheral interface) modules 5 4 crc (cyclic redundancy check) unit 2 1
introduction spc56xp54x, spc56xp60x 10/104 doc id 18340 rev 3 figure 1. spc56xp54/60 block diagram cross bar switch (xbar, amba 2.0 v6 ahb) xbar_0 flexray e200z0 core peripheral bus (ips) 32-bit nexus port controller general purpose registers pmu variable length encoded instructions integer execution unit mc_cgm adc_0 ctu_0 etimer_0 etimer_1 dspi_0 dspi_1 dspi_2 dspi_3 linflex_0 linflex_1 flexcan_0 safetyport_0 wakeup cmu_0 cmu_1 fmpll ircosc mc_rgm xosc flexcan_1 dspi_4 fccu_0 peripheral bus (ips) intc_0 swt_0 stm_0 ecsm_0 sema4_0 dmamux_0 dma_0 special purpose registers branch prediction unit load/store unit jtag nexus 2+ exception handler instruction unit siul crc_0 bam pit sscm 48kb sram with ecc pbridge_0 nasps_0 sramc_0 1024kb code flash with ecc 4x16kb data flash with ecc pflashc_0 e200z0 core 32-bit general purpose registers variable length encoded instructions integer execution unit special purpose registers branch prediction unit load/store unit jtag nexus 2+ exception handler instruction unit intc_1 swt_1 stm_1 ecsm_1 sema4_1 memory protection unit mpu_0 memory protection unit mpu_1 32kb sram with ecc nasps_1 pbridge_1 sramc_1 m2 m3 m0 m1 m5 m6 s7 s2 s0 s1 s3 s6 p0 p1 data data instr instr crc_1 26 mc_pcu mc_me
spc56xp54x, spc56xp60x introduction doc id 18340 rev 3 11/104 table 4. spc56xp54/60 series block summary block function analog-to-digital converter (adc) multi-channel, 10-bit analog-to-digital converter boot assist module (bam) block of read-only memory containing vle code which is executed according to the boot mode of the device clock generation module (mc_cgm) provides logic and control required for the generation of system and peripheral clocks controller area network (flexcan) supports the standard can communications protocol cross triggering unit (ctu) enables synchronization of adc conversi ons with a timer event from the emios or from the pit crossbar switch (xbar) supports simultaneous connections between two master ports and three slave ports. the crossbar supports a 32-bit address bus width and a 32-bit data bus width. cyclic redundancy checker (crc) unit is dedicated to the computation of crc off-loading the cpu. each context has a separate crc computation engine in order to allow the concurrent computation of the crc of multiple data streams. deserial serial peripheral interface (dspi) provides a synchronous serial interface for communication with external devices enhanced direct memory access (edma) performs complex data transfers with minimal intervention from a host processor via ? n ? programmable channels enhanced timer (etimer) provides enhanced programmable up/down modulo counting error correction status module (ecsm) provides a myriad of miscellaneous cont rol functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory erro rs reported by error-correcting codes external oscillator (xosc) provides an output clock used as input reference for fmpll_0 or as reference clock for specific modules depending on system needs fault collection and control unit (fccu) provides functional safety to the device flash memory provides non-volatile storage for program code, constants and variables flexray (flexray communication controller) provides high-speed distributed contro l for advanced automotive applications frequency-modulated phase- locked loop (fmpll) generates high-speed system clocks and supports programmable frequency modulation interrupt controller (intc) provides priority-bas ed preemptive scheduling of interrupt requests jtag controller provides the means to test chip functi onality and connectivity while remaining transparent to system logic when not in test mode linflex controller manages a high number of lin (local interconnect network protocol) messages efficiently with a minimum of cpu load mode entry module (mc_me) provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manage s the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications
introduction spc56xp54x, spc56xp60x 12/104 doc id 18340 rev 3 peripheral bridge (pbridge) is the interface between the system bus and on-chip peripherals periodic interrupt timer (pit) produces periodic interrupts and triggers power control unit (mc_pcu) reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called ?power domains? which are controlled by the pcu reset generation module (mc_rgm) centralizes reset sources and manages the device reset sequence of the device semaphore unit (sema4) provides the hardware support needed in multi-core systems for implementing semaphores and provide a simple mechanism to achieve lock/unlock operations via a single write access static random-access memory (sram) provides storage for program code, constants, and variables system integration unit lite (siul) provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration system status and configuration module (sscm) provides system configuration and status data (such as memory size and status, device mode and security status ), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable system timer module (stm) provides a set of output compare events to support autosar (1) and operating system tasks system watchdog timer (swt) provides protection from runaway code wakeup unit (wkpu) supports up to 18 external sources that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests or wakeup events. 1. autosar: automotive open system architecture (see www.autosar.org) table 4. spc56xp54/60 series block summary (continued) block function
spc56xp54x, spc56xp60x introduction doc id 18340 rev 3 13/104 1.5 feature details 1.5.1 high performance e200z0h core processor the e200z0h power architecture core provides the following features: high performance e200z0 core processor for managing peripherals and interrupts single issue 4-stage pipeline in-order execution 32-bit power architecture cpu harvard architecture variable length encoding (vle), allowing mixed 16-bit and 32-bit instructions ? results in smaller code size footprint ? minimizes impact on performance branch processing acceleration using lookahead instruction buffer load/store unit ? 1-cycle load latency ? misaligned access support ? no load-to-use pipeline bubbles thirty-two 32-bit general purpose registers (gprs) separate instruction bus and load/store bus harvard architecture hardware vectored interrupt support reservation instructions for implementing read-modify-write constructs long cycle time instructions, except for guarded loads, do not increase interrupt latency extensive system development support through nexus debug port non maskable interrupt support 1.5.2 crossbar switch (xbar) the xbar multi-port crossbar switch supports simultaneous connections between six master ports and six slave ports. the crossbar supports a 32-bit address bus width and a 32-bit data bus width. the crossbar allows for two concurrent transactions to occur from any master port to any slave port; but one of those transfers must be an instruction fetch from internal flash memory. if a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grant it ownership of the slave port. all other masters requesting that slave port are stalled until the higher priority master completes its transactions. re questing masters are treated wit h equal priority and will be granted access to a slave port in round-robin fashion, based upon the id of the last master to be granted access.
introduction spc56xp54x, spc56xp60x 14/104 doc id 18340 rev 3 the crossbar provides the following features: 6 master ports: ? 2 e200z0 core comp lex instruction ports ? 2 e200z0 core complex load/store data ports ?edma ?flexray 6 slave ports: ? 2 flash memory (code flash and data flash) ? 2 sram (48 kb + 32 kb) ? 2 pbridge 32-bit internal address, 32-bit internal data paths fixed priority arbitration based on port master temporary dynamic priority elevation of masters 1.5.3 enhanced direct memory access (edma) the enhanced direct memory access (edma) controller is a second-generation module capable of performing complex data movements via 16 programmable channels, with minimal intervention from the host processor. the hardware micro architecture includes a dma engine which performs source and destination address calculations, and the actual data movement operations, along with an sram-based memory containing the transfer control descriptors (tcd) for the channels. this implementation is utilized to minimize the overall block size. the edma module provides the following features: 16 channels support independent 8, 16 or 32-bit single value or block transfers supports variable sized queues and circular queues source and destination address registers are independently configured to post- increment or remain constant each transfer is initiated by a peripheral, cpu, or edma channel request each edma channel can optionally send an interrupt request to the cpu on completion of a single value or block transfer dma transfers possible between system me mories, dspis, adc, etimer and ctu programmable dma channel multiplexer for assignment of any dma source to any available dma channel with up to 30 potential request sources edma abort operation through software 1.5.4 on-chip flash memory with ecc the spc56xp54/60 provides up to 1024 kb of programmable, non-volatile, flash memory. the non-volatile memory (nvm) can be used for instruction and/or data storage. the flash memory module interfaces the system bus to a dedicated flash memory array controller. it supports a 32-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory. the module contains a four-entry, 4x128-bit prefetch buffers. prefetch buffer hits allow no-wait responses. normal flash memory array accesses are registered and are forwarded to the system bus on the following cycle, incurring 2 wait states.
spc56xp54x, spc56xp60x introduction doc id 18340 rev 3 15/104 the flash memory module provides the following features: up to 1024 kb flash memory ? 14 blocks (216 kb + 232 kb + 216 kb + 264 kb + 6128 kb) code flash ? 4 blocks (16 kb + 16 kb + 16 kb + 16 kb) data flash ? full read while write (rww) cap ability between code and data flash four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch buffers can be configured to prefetch code or data or both) typical flash memory access time: 0 wait states for buffer hits, 2 wait states for page buffer miss at 64 mhz hardware managed flash memory writes handled by 32-bit risc krypton engine hardware and software configurable read and write access protections on a per-master basis. configurable access timing allowing use in a wide range of system frequencies. multiple-mapping support and mapping-based block access timing (0?31 additional cycles) allowing use for emulation of other memory types. software programmable block program/erase restriction control. erase of selected block(s) read page size of 128 bits (4 words) 64-bit ecc with single-bit correction, do uble-bit detection for data integrity embedded hardware program and erase algorithm erase suspend, program suspend and erase-suspended program censorship protection scheme to prev ent flash memory content visibility hardware support for eeprom emulation 1.5.5 on-chip sram with ecc the spc56xp54/60 sram module provides a general-purpose memory of up to 80 kb. the sram module provides the following features: supports read/write accesses mapped to the sram memory from any master up to 80 kb general purpose ram ? 2 blocks (48 kb + 32 kb) supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory typical sram access time: 0 wait state for reads and 32-bit writes; 1 wait state for 8- and 16-bit writes if back to back with a read to same memory block 1.5.6 interrupt controller (intc) the intc (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. for high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (isr) has been minimized. the intc provides a unique vector for each interrupt request source for quick determination of which isr needs to be executed. it also provides an ample number of priorities so that lower priority isrs do not delay the execution of higher priority isrs. to
introduction spc56xp54x, spc56xp60x 16/104 doc id 18340 rev 3 allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable. when multiple tasks share a resource, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol for coherent accesses. by providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. the intc provides the following features: unique 9-bit vector for each separate interrupt source 8 software triggerable interrupt sources 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source ability to modify the is r or task priority. ? modifying the priority can be used to implement the priority ceiling protocol for accessing shared resources. 2 external high priority interrupts directly accessing the main core and iop critical interrupt mechanism the intc module is replicated for each processor. 1.5.7 system clocks and clock generation the following list summarizes the system clock and clock generation on the spc56xp54/60: lock detect circuitry continuously monitors lock status loss of clock (loc) detection for pll outputs programmable output clock divider ( ? 1, ? 2, ? 4, ? 8) programmable output clock divider ( ? 1, ? 2, ? 3 to ? 256) etimer module running at the same frequency as the e200z0h core on-chip oscillator with au tomatic level control internal 16 mhz rc oscillator for rapid start-up and safe mode ? supports frequency trimming by user application 1.5.8 frequency modulated phase-locked loop (fmpll) the fmpll allows the user to generate high speed system clocks from a 4 mhz to 40 mhz input clock. further, the fmpll supports programmable frequency modulation of the system clock. the fmpll multiplication factor, output clock divider ratio are all software configurable.
spc56xp54x, spc56xp60x introduction doc id 18340 rev 3 17/104 the fmpll has the following major features: input clock frequency from 4 mhz to 40 mhz voltage controlled oscillator (vco ) range from 256 mhz to 512 mhz reduced frequency divider (rfd) for reduced frequency operation without forcing the pll to relock modulation enabled/disabled through software triangle wave modulation programmable modulation depth (0.25% to 4% deviation from center frequency) ? programmable modulation frequency dependent on reference frequency self-clocked mode (scm) operation 1.5.9 main oscillator the main oscillator prov ides these features: input frequency range 4 mhz to 40 mhz crystal input mode or oscillator input mode pll reference 1.5.10 internal rc oscillator this device has an rc ladder phas e-shift oscillator. the architec ture uses constant current charging of a capacitor. the voltage at the capacitor is compared by the stable bandgap reference voltage. the rc oscillator provides these features: nominal frequency 16 mhz 6% variation over voltage and temperature after process trim clock output of the rc oscillato r serves as system clock sour ce in case loss of lock or loss of clock is detected by the pll rc oscillator is used as the de fault system clock during startup 1.5.11 periodic inte rrupt timer (pit) the pit module implements these features: up to four general purpose interrupt timers 32-bit counter resolution clocked by system clock frequency each channel can be used as trigger for a dma request 1.5.12 system ti mer module (stm) the stm module implements these features: 32-bit up counter with 8-bit prescaler four 32-bit compare channels independent interrupt source for each channel counter can be stopped in debug mode the stm module is replicated for each processor.
introduction spc56xp54x, spc56xp60x 18/104 doc id 18340 rev 3 1.5.13 software wa tchdog timer (swt) the swt has the following features: fault tolerant output safe internal rc oscillator as reference clock windowed watchdog program flow control monitor with 16-bit pseudorandom key generation the swt module is replicated for each processor. 1.5.14 fault collection and control unit (fccu) the fccu provides an independent fault report ing mechanism even if the cpu is exhibiting unstable behaviors. the fccu modu le has the following features: redundant collection of hardware checker results redundant collection of error information and latch of faults from critical modules on the device collection of se lf-test results configurable and graded fault control ? internal reactions (no internal reaction, irq) ? external reaction (failure is reported to the external/surrounding system via configurable output pins) 1.5.15 system inte gration unit (siul) the spc56xp54/60 siul controls mcu pad configuration, external interrupts, general purpose i/o (gpio) pin configuration, and internal peripheral multiplexing. the pad configuration block controls the static electrical characteristics of i/o pins. the gpio block provides uniform and discrete input/output control of the i/o pins of the mcu. the siul provides the following features: centralized general purpose input output (gpio) control of input/output pins and analog input-only pads (package dependent) all gpio pins can be independently configured to support pull-up, pull down, or no pull reading and writing to gpio supported both as individual pins and 16-bit wide ports all peripheral pins (except adc channels) can be alternatively configured as both general purpose input or output pins adc channels support alternative configuration as general purpose inputs direct readback of the pin value is supported on all pins through the siu configurable digital input filter that can be applied to some general purpose input pins for noise elimination ? up to 4 internal functions can be multiplexed onto one pin 1.5.16 boot and censorship different booting modes are available in the spc56xp54/60: from internal flash memory via a serial link
spc56xp54x, spc56xp60x introduction doc id 18340 rev 3 19/104 the default booting scheme is the one which us es the internal flash memory (an internal pull-down is used to select this mode). the alternate option allows the user to boot via flexcan or linflex (using the boot assist module software). a censorship scheme is provided to protect the contents of the flash memory and offer increased security for the entire device. a password mechanism is designed to grant th e legitimate user access to the non-volatile memory. boot assist module (bam) the bam is a block of read-only one-time programmed memory and is identical for all spc56xp54/60 devices that are based on the e200z0h core. the bam program is executed every time the device is powered on if the alternate boot mode has been selected by the user. the bam provides the following features: serial bootloading via flexcan or linflex. bam can accept a password via the used serial communication channel to grant the legitimate user access to the non-volatile memory. 1.5.17 error correctio n status module (ecsm) the ecsm on this device features the following: platform configuration and revision ecc error reporting for flash memory and sram ecc error injection for sram the ecsm module is replicated for each processor. 1.5.18 flexcan the flexcan module is a communication controller implementing the can protocol according to bosch specification version 2.0b. the can protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real- time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness and required bandwidth. flexcan module contains 32 message buffers.
introduction spc56xp54x, spc56xp60x 20/104 doc id 18340 rev 3 the flexcan module provides the following features: full implementation of the can protocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? 0 to 8 bytes data length ? programmable bit rate as fast as 1 mbit/s 32 message buffers of 0 to 8 bytes data length each message buffer configurable as rx or tx, all supporting standard and extended messages programmable loop-back mode supporting self-test operation 3 programmable mask registers programmable transmit-first scheme: lowest id or lowest buffer number time stamp based on 16-bit free-running timer global network time, synchronized by a specific message maskable interrupts independent of the transmission medium (an external transceiver is assumed) high immunity to emi short latency time due to an arbitration scheme for high-priority messages transmit features ? supports configuration of multiple mailboxes to form message queues of scalable depth ? arbitration scheme according to message id or message buffer number ? internal arbitration to guarantee no inner or outer priority inversion ? transmit abort procedure and notification receive features ? individual programmable filters for each mailbox ? 8 mailboxes configurable as a six-entry receive fifo ? 8 programmable acceptance filters for receive fifo programmable clock source ? system clock ? direct oscillator clock to avoid pll jitter 1.5.19 safety port (flexcan) the spc56xp54/60 mcu has a second can controller synthesized to run at high bit rates to be used as a safety port. the can module of the safety port provides the following features: identical to the flexcan module bit rate as fast as 7.5 mb at 60 mhz cpu clock using direct connection between can modules (no physical transceiver required) 32 message buffers of 0 to 8 bytes data length can be used as a third independent can module
spc56xp54x, spc56xp60x introduction doc id 18340 rev 3 21/104 1.5.20 flexray the flexray module provides the following features: full implementation of flexray protocol specification 2.1 64 configurable message buffers can be handled dual channel or single channel mode of operation, each as fast as 10 mbit/s data rate message buffers configurable as tx, rx or rxfifo message buffer size configurable message filtering for all message buffers based on frameid, cycle count and message id programmable acceptance filters for rxfifo message buffers 1.5.21 serial communication interface module (linflex) the linflex on the spc56xp54/60 features the following: supports lin master mode (on both modules), lin slave mode (on one module) and uart mode lin state machine compliant to lin1.3, 2.0, and 2.1 specifications handles lin frame transmission and reception without cpu intervention lin features ? autonomous lin frame handling ? message buffer to store identifier and up to 8 data bytes ? supports message length as long as 64 bytes ? detection and flagging of lin errors: sync field; delimiter; id parity; bit; framing; checksum and time-out errors ? classic or extended checksum calculation ? configurable break duration as long as 36-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features: loop back; self test; lin bus stuck dominant detection ? interrupt-driven operation with 16 interrupt sources lin slave mode features ? autonomous lin header handling ? autonomous lin response handling uart mode ? full-duplex operation ? standard non return-to-zero (nrz) mark/space format ? data buffers with 4-byte receive, 4-byte transmit ? configurable word length (8-bit or 9-bit words) ? error detection and flagging ? parity, noise and framing errors ? interrupt-driven operation with four interrupt sources ? separate transmitter and receiver cpu interrupt sources ? 16-bit programmable baud-rate modulus counter and 16-bit fractional ? 2 receiver wake-up methods
introduction spc56xp54x, spc56xp60x 22/104 doc id 18340 rev 3 1.5.22 deserial serial peripheral interface (dspi) the deserial serial peripheral interface (dspi) module provides a synchronous serial interface for communication between the spc56xp54/60 mcu and external devices. the dspi modules provide these features: full duplex, synchronous transfers master or slave operation programmable master bit rates programmable clock polarity and phase end-of-transmission interrupt flag programmable transfer baud rate programmable data frames from 4 to 16 bits up to 28 chip select lines available ? 8 each on dspi_0 and dspi_1 ? 4 each on dspi_2, dspi_3, and dspi_4 8 clock and transfer attributes registers chip select strobe available as alternate function on one of the chip select pins for deglitching fifos for buffering up to 5 transfers on the transmit and receive side queueing operation possible through use of the edma general purpose i/o functionality on pins when not used for spi 1.5.23 etimer two etimer modules are provided, each with six 16-bit general purpose up/down timer/counter per module. the following features are implemented: individual channel capability ? input capture trigger ? output compare ? double buffer (to capture rising edge and falling edge) ? separate prescaler for each counter ? selectable clock source ? 0% to 100% pulse measurement ? rotation direction flag (quad decoder mode) maximum count rate ? equals peripheral clock/2 ? for external event counting ? equals peripheral clock ? for internal clock counting cascadeable counters programmable count modulo quadrature deco de capabilities counters can share available input pins count once or repeatedly preloadable counters pins available as gpio when timer functionality not in use
spc56xp54x, spc56xp60x introduction doc id 18340 rev 3 23/104 1.5.24 analog-to-digi tal converter (adc) the adc module provides the following features: analog part: 1 on-chip analog-to-digital converter 10-bit ad resolution 1 sample and hold unit per adc conversion time, including sampling time, less than 1 ? s (at full precision) typical sampling time is 150 ns min. (at full precision) differential non-linearit y error (dnl) 1 lsb integral non-linearity error (inl) 1.5 lsb total unadjusted error (tue) <3 lsb single-ended input signal range from 0 to 3.3 v / 5.0 v adc and its reference can be supplied with a voltage independent from v ddio adc supply can be equal or higher than v ddio adc supply and the adc reference are not independent from each other (they are internally bonded to the same pad) sample times of 2 (default), 8, 64, or 128 adc clock cycles digital part: 27 input channels (26 + 1 internally connected) 4 analog watchdogs to compare adc results against predefined levels (low, high, range) before results are stored 2 operating modes: normal mode and ctu control mode normal mode features ? register-based interface with the cpu: control register, status register, 1 result register per channel ? adc state machine managing 3 request flows: regular command, hardware injected command, and software injected command ? selectable priority between software and hardware injected commands ? dma compatible interface ctu control mode features ? triggered mode only ? 4 independent result queues (2 16 entries, 2 4 entries) ? result alignment circuitry (lef t justified; ri ght justified) ? 32-bit read mode allows to have channel id on one of the 16-bit part ? dma compatible interfaces 1.5.25 cross trigge ring unit (ctu) the cross triggering unit (ctu) allows automa tic generation of adc conversion requests on user selected conditions with minimized cpu load for dynamic configuration.
introduction spc56xp54x, spc56xp60x 24/104 doc id 18340 rev 3 it implements the following features: double buffered trigger generation unit with up to eight independent triggers generated from external triggers trigger generation unit configurable in sequential mode or in triggered mode each trigger can be appropriately delayed to compensate the delay of external low pass filter double buffered global trigger unit allowing etimer synchronization and/or adc command generation double buffered adc command list pointers to minimize adc-trigger unit update double buffered adc conversion command list with up to 24 adc commands each trigger has the capability to generate consecutive commands adc conversion command allows to control adc channel from each adc, single or synchronous sampling, independent result queue selection 1.5.26 cyclic redundancy check (crc) 3 contexts for the conc urrent crc computation separate crc engine for each context zero-wait states during the crc computation (pipeline scheme) 3 hard-wired polynomials (crc-8 vda can, crc-32 ethern et and crc-16-ccitt) support for byte/half-word/word width of the input data stream support for expected and actual crc comparison 1.5.27 nexus develop ment interface (ndi) the ndi block provides real-time developmen t support capabilities fo r the spc56xp54/60 power architecture based m cu in compliance with the ieee- isto 5001-2003 standard. this development support is supplied for mcus without requiring external address and data pins for internal visibility. the ndi block is an integration of several individual nexus blocks that are selected to provide the development support interface for this device. the ndi block interfaces to the host processor and internal buses to provide development support as per the ieee-isto 5001-2003 class 2+ standard. the de velopment support provided includes access to the mcu?s internal memory map and access to the processor?s internal registers during run time.
spc56xp54x, spc56xp60x introduction doc id 18340 rev 3 25/104 the nexus interface provides the following features: configured via the ieee 1149.1 all nexus port pins operate at v ddio (no dedicated power supply) nexus 2+ features supported ? static debug ? watchpoint messaging ? ownership trace messaging ? program trace messaging ? real time read/write of any internally memory mapped resources through jtag pins ? overrun control, which selects whether to stall before nexus overruns or keep executing and allow overwrite of information ? watchpoint triggering, watchpoint triggers program tracing ?ddr auxiliary output port ? 4 mdo (message data out) pins ? mcko (message clock out) pin ? 2 mseo (message start/end out) pins ?evto (event out) pin auxiliary input port ?evti (event in) pin 1.5.28 ieee 1149.1 (jtag) controller the jtag controller (jtagc) block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. all data input to and output from the jtagc block is communicated in serial format. the jtagc block is compliant with the ieee standard. the jtag controller provides the following features: ieee test access port (tap) interface with four pins (tdi, tms, tck, tdo) selectable modes of operation include jtagc/debug or normal system operation. a 5-bit instruction register that supports the following ieee 1149.1-2001 defined instructions: ? bypass, idcode, extest, sample, sample/preload a 5-bit instruction register that supports the additional followin g public instructions: ? access_aux_tap_npc, access_aux_tap_core0, access_aux_tap_core1, access_aux_tap_nasps_0, access_aux_tap_nasps_1 three test data registers: a bypass register, a boundary scan register, and a device identification register. a tap controller state machine that controls the operation of the data registers, instruction register and associated circuitry.
introduction spc56xp54x, spc56xp60x 26/104 doc id 18340 rev 3 1.5.29 on-chip voltage regulator (vreg) the on-chip voltage regulator module provides the following features: uses external npn transistor regulates external 3.3 v to 5.0 v down to 1.2 v for the core logic low voltage detection on the internal 1.2 v and i/o voltage 3.3 v
spc56xp54x, spc56xp60x package pinouts and signal descriptions doc id 18340 rev 3 27/104 2 package pinouts and signal descriptions 2.1 package pinouts the lqfp pinouts are shown in the following figures. figure 2. lqfp176 pinout (top view) (a) a. software development package onl y. not available for production. pa[15] pa[14] pc[6] pg[1] rdy mdo11 v ss_hv_io4 v dd_hv_io4 pd[2] pf[3] mdo10 nc nc nc pb[6] pf[2] pa[13] pf[1] pa[9] pf[0] v ss_lv_cor2 v dd_lv_cor2 pc[8] pd[4] pd[3] v ss_hv_io3 v dd_hv_io3 pd[0] pc[15] pc[9] pa[12] pe[15] pa[11] pe[14] pa[10] pe[13] pb[3] pf[14] pb[2] pf[15] pf[13] pc[10] pb[1] pb[0] pd[7] pg[0] pe[1] pe[3] pc[1] pe[4] pb[7] pe[5] pc[2] pe[6] pb[8] pe[7] pe[2] nc v reg_bypass pb[9] pb[10] pb[11] pb[12] v dd_hv_ad v ss_hv_ad pd[15] pe[8] pb[13] pe[9] pb[15] nc nc nc nc pe[10] pb[14] pe[11] pc[0] pe[12] pe[0] bctrl v dd_lv_regcor nc nc v ss_lv_regcor v dd_hv_reg nc nc pa[4] v pp_test pf[12] pd[14] pg[3] pc[14] pg[2] pc[13] pg[4] pd[12] pg[6] v dd_hv_fl v ss_hv_fl pd[13] v ss_lv_cor1 v dd_lv_cor1 pa[3] v dd_hv_io2 v ss_hv_io2 nc mdo9 mdo8 mdo7 v ss_hv_io6 v dd_hv_io6 tdo tck tms tdi pg[5] pa[2] pg[7] pc[12] nc nc pg[8] pc[11] pg[9] pd[11] pg[10] pd[10] pg[11] pa[1] pa[0] nmi pa[6] pd[1] pf[4] v dd_hv_io5 v ss_hv_io5 mdo4 mdo5 mdo6 nc nc nc pf[5] v dd_hv_io0 v ss_hv_io0 pf[6] mdo0 pa[7] pc[4] pa[8] pc[5] pa[5] pc[7] pc[3] v ss_lv_cor0 v dd_lv_cor0 pf[7] pf[8] v dd_hv_io1 v ss_hv_io1 pf[9] pf[10] pf[11] pd[9] v dd_hv_osc v ss_hv_osc xtal extal reset pd[8] pd[5] pd[6] v ss_lv_cor3 v dd_lv_cor3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 lqfp176
package pinouts and signal descriptions spc56xp54x, spc56xp60x 28/104 doc id 18340 rev 3 figure 3. lqfp144 pinout (top view) (b) b. availability of port pin alternate functions depends on product selection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 nmi pa [ 6 ] pd[1] pf[4] pf[5] v dd_hv_io0 v ss_hv_io0 pf[6] mdo pa [ 7 ] pc[4] pa [ 8 ] pc[5] pa [ 5 ] pc[7] pc[3] v ss_lv_cor0 v dd_lv_cor0 pf[7] pf[8] v dd_hv_io1 v ss_hv_io1 pf[9] pf[10] pf[11] pd[9] v dd_hv_osc v ss_hv_osc xtal extal reset pd[8] pd[5] pd[6] v ss_lv_cor3 v dd_lv_cor3 pa [ 4 ] v pp_test pf[12] pd[14] pg[3] pc[14] pg[2] pc[13] pg[4] pd[12] pg[6] v dd_hv_fl v ss_hv_fl pd[13] v ss_lv_cor1 v dd_lv_cor1 pa [ 3 ] v dd_hv_io2 v ss_hv_io2 tdo tck tms tdi pg[5] pa [ 2 ] pg[7] pc[12] pg[8] pc[11] pg[9] pd[11] pg[10] pd[10] pg[11] pa [ 1 ] pa [ 0 ] pd[7] pg[0] pe[1] pe[3] pc[1] pe[4] pb[7] pe[5] pc[2] pe[6] pb[8] pe[7] pe[2] nc v reg_bypass pb[9] pb[10] pb[11] pb[12] v dd_hv_ad v ss_hv_ad pd[15] pe[8] pb[13] pe[9] pb[15] pe[10] pb[14] pe[11] pc[0] pe[12] pe[0] bctrl v dd_lv_regcor v ss_lv_regcor v dd_hv_reg pa [ 1 5 ] pa [ 1 4 ] pc[6] pg[1] pd[2] pf[3] pb[6] pf[2] pa [ 1 3 ] pf[1] pa [ 9 ] pf[0] v ss_lv_cor2 v dd_lv_cor2 pc[8] pd[4] pd[3] v ss_hv_io3 v dd_hv_io3 pd[0] pc[15] pc[9] pa [ 1 2 ] pe[15] pa [ 1 1 ] pe[14] pa [ 1 0 ] pe[13] pb[3] pf[14] pb[2] pf[15] pf[13] pc[10] pb[1] pb[0] lqfp144
spc56xp54x, spc56xp60x package pinouts and signal descriptions doc id 18340 rev 3 29/104 figure 4. lqfp100 pinout (top view) (c) 2.2 pin descriptions the following sections provide signal descriptions and related information about the functionality and configuration of the spc56xp54/60 devices. 2.2.1 power supply and reference voltage pins ta bl e 5 lists the power supply and reference voltage for the spc56xp54/60 devices. c. availability of port pi n alternate functions depends on product selection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 nmi pa [ 6 ] pd[1] pa [ 7 ] pc[4] pa [ 8 ] pc[5] pa [ 5 ] pc[7] pc[3] v ss_lv_cor0 v dd_lv_cor0 v dd_hv_io1 v ss_hv_io1 pd[9] v dd_hv_osc v ss_hv_osc xtal extal reset pd[8] pd[5] pd[6] v ss_lv_cor3 v dd_lv_cor3 pa [ 4 ] v pp test pd[14] pc[14] pc[13] pd[12] v dd_hv_fl v ss_hv_fl pd[13] v ss_lv_cor1 v dd_lv_cor1 pa [ 3 ] v dd_hv_io2 v ss_hv_io2 tdo tck tms tdi pa [ 2 ] pc[12] pc[11] pd[11] pd[10] pa [ 1 ] pa [ 0 ] pd[7] pe[1] pc[1] pb[7] pc[2] pb[8] pe[2] nc v reg_bypass pb[9] pb[10] pb[11] pb[12] v dd_hv_ad v ss_hv_ad pd[15] pb[13] pb[15] pb[14] pc[0] pe[0] bctrl v dd_lv_regcor v ss_lv_regcor v dd_hv_reg pa[15] pa[14] pc[6] pd[2] pb[6] pa[13] pa [ 9 ] v ss_lv_cor2 v dd_lv_cor2 pc[8] pd[4] pd[3] v ss_hv_io3 v dd_hv_io3 pd[0] pc[15] pc[9] pa[12] pa[11] pa[10] pb[3] pb[2] pc[10] pb[1] pb[0] lqfp100 table 5. supply pins supply pin symbol description lqfp 100 lqfp 144 lqfp 176 (1) vreg control and power supply pins bctrl voltage regulator external npn ballast base control pin 47 69 81 v dd_hv_reg (3.3 v or 5.0 v) voltage regulator supply voltage 50 72 86
package pinouts and signal descriptions spc56xp54x, spc56xp60x 30/104 doc id 18340 rev 3 v dd_lv_regcor 1.2 v decoupling (2) pins for core logic supply and voltage regulator feedback. decoupling capacitor must be connected between this pins and v ss_lv_regcor. 48 70 82 v ss_lv_regcor 1.2 v decoupling (2) pins for core logic gnd and voltage regulator feedback. decoupling capacitor must be connected between this pins and v dd_lv_regcor. 49 71 85 adc0 reference and supply voltage v dd_hv_ad adc supply and high reference voltage 39 56 64 v ss_hv_ad adc ground and low reference voltage 40 57 65 power supply pins (3.3 v or 5.0 v) v dd_hv_io0 input/output supply voltage ? 6 14 v ss_hv_io0 input/output ground ? 7 15 v dd_hv_io1 input/output supply voltage 13 21 29 v ss_hv_io1 input/output ground 14 22 30 v dd_hv_io2 input/output supply voltage 63 91 115 v ss_hv_io2 input/output ground 62 90 114 v dd_hv_io3 input/output supply voltage 87 126 150 v ss_hv_io3 input/output ground 88 127 151 v dd_hv_io4 input/output supply voltage ? ? 169 v ss_hv_io4 input/output ground ? ? 170 v dd_hv_io5 input/output supply voltage ? ? 5 v ss_hv_io5 input/output ground ? ? 6 v dd_hv_io6 input/output supply voltage ? ? 108 v ss_hv_io6 input/output ground ? ? 109 v dd_hv_fl code and data flash supply voltage 69 97 121 v ss_hv_fl code and data flash supply ground 68 96 120 v dd_hv_osc crystal oscillator amplifier supply voltage 16 27 35 v ss_hv_osc crystal oscillator amplifier ground 17 28 36 power supply pins (1.2 v) v dd_lv_cor0 1.2 v decoupling pins for core logic supply. decoupling capacitor must be connected between t hese pins and the nearest v ss_lv_cor0 pin. 12 18 26 v ss_lv_cor0 1.2 v decoupling pins for core logic gnd. decoupling capacitor must be connected between t hese pins and the nearest v dd_lv_cor0 pin . 11 17 25 table 5. supply pins (continued) supply pin symbol description lqfp 100 lqfp 144 lqfp 176 (1)
spc56xp54x, spc56xp60x package pinouts and signal descriptions doc id 18340 rev 3 31/104 2.2.2 system pins ta bl e 6 and ta b l e 7 contain information on pin functions for the spc56xp54/60 devices. the pins listed in ta b l e 6 are single-function pins. the pins shown in ta bl e 7 are multi-function pins, programmable via their respective pad configuration register (pcr) values. v dd_lv_cor1 1.2 v decoupling pins for core logic supply. decoupling capacitor must be connected between t hese pins and the nearest v ss_lv_cor1 pin. 65 93 117 v ss_lv_cor1 1.2 v decoupling pins for core logic gnd. decoupling capacitor must be connected between t hese pins and the nearest v dd_lv_cor1 pin. 66 94 118 v dd_lv_cor2 1.2 v decoupling pins for core logic supply. decoupling capacitor must be connected between t hese pins and the nearest v ss_lv_cor2 pin. 92 131 155 v ss_lv_cor2 1.2 v decoupling pins for core logic gnd. decoupling capacitor must be connected between t hese pins and the nearest v dd_lv_cor 2 pin. 93 132 156 v dd_lv_cor3 1.2 v decoupling pins for core logic supply. decoupling capacitor must be connected between t hese pins and the nearest v ss_lv_cor3 pin. 25 36 44 v ss_lv_cor3 1.2 v decoupling pins for core logic gnd. decoupling capacitor must be connected between t hese pins and the nearest v dd_lv_cor 3 pin. 24 35 43 1. lqfp176 available only as development package. 2. see datasheet voltage regulator electrical c haracteristics secti on for more details. table 5. supply pins (continued) supply pin symbol description lqfp 100 lqfp 144 lqfp 176 (1) table 6. system pins symbol description direction pad speed (1) pin src=0 src=1 lqfp 100 lqfp 144 lqfp 176 (2) dedicated pins mdo0 nexus message data output?line 0 output only fast ? 9 17 mdo4 nexus message data output?line 4 output only fast ? ? 7 mdo5 nexus message data output?line 5 output only fast ? ? 8 mdo6 nexus message data output?line 6 output only fast ? ? 9
package pinouts and signal descriptions spc56xp54x, spc56xp60x 32/104 doc id 18340 rev 3 mdo7 nexus message data output?line 7 output only fast ? ? 110 mdo8 nexus message data output?line 8 output only fast ? ? 111 mdo9 nexus message data output?line 9 output only fast ? ? 112 mdo10 nexus message data output?line 10 output only fast ? ? 166 mdo11 nexus message data output?line 11 output only fast ? ? 171 rdy nexus ready output output only ? ? ? ? 172 nmi non-maskable interrupt input only ? ? 1 1 1 xtal analog output of the oscillator amplifier circuit. needs to be grounded if oscillator is used in bypass mode. ???182937 extal analog input of the oscillator amplifier circuit, when the oscillator is not in bypass mode. analog input for the clock generator when the oscillator is in bypass mode. ???193038 tms (3) jtag state machine control input only ? ? 59 87 105 tck (3) jtag clock input only ? ? 60 88 106 tdi (3) jtag data input input only ? ? 58 86 104 tdo (3) jtag data output output only ? ? 61 89 107 reset pin reset (4) bidirectional reset with schmitt trigger characteristics and noise filter bidirec- tional medium ? 20 31 39 test pin v pp test pin for testing purpose only. to be tied to ground in normal operating mode. ? ? ? 74 107 131 v reg_bypass pin for testing purpose only. to be tied to ground in normal operating mode. ???345159 1. src values refer to the value assigned to the slew ra te control bits of the pad configuration register. 2. lqfp176 available only as development package. 3. in this pin there is an internal pull, refer to jtag c chapter in the device refer ence manual for pull direction. 4. its configuration can be set up by the pcr[108] register in side the siu module. see siul c hapter in the device reference manual. table 6. system pins (continued) symbol description direction pad speed (1) pin src=0 src=1 lqfp 100 lqfp 144 lqfp 176 (2)
spc56xp54x, spc56xp60x package pinouts and signal descriptions doc id 18340 rev 3 33/104 2.2.3 pin muxing ta bl e 7 defines the pin list and muxing for the spc56xp54/60 devices relative to full- featured version. each row of ta bl e 7 shows all the possible ways of configuring each pin, via ?alternate functions?. the default function assigned to each pin after reset is the alt0 function. pins marked as external interrupt capable can also be used to resume from stop and halt mode. spc56xp54/60 devices provide four main i/o pad types depending on the associated functions: slow pads are the most common, providing a compromise between transition time and low electromagnetic emission. medium pads provide fast enough transition for serial communication channels with controlled current to reduce electromagnetic emission. fast pads provide maximum speed. they are used for improved nexus debugging capability. symmetric pads are designed to meet flexray requirements. medium and fast pads can use slow configur ation to reduce electromagnetic emission, at the cost of reducing ac performance. table 7. pin muxing (1) port pin pcr register alternate function (2),(3) functions peripheral (4) i/o direction (5) pad speed (6) pin src = 0 src = 1 lqfp 100 lqfp 144 lqfp 176 (7) port a a[0] pcr[0] alt0 alt1 alt2 alt3 ? gpio[0] etc[0] sck_2 f[0] eirq[0] siul etimer_0 dspi_2 fccu siul i/o i/o i/o o i slow medium 51 73 89 a[1] pcr[1] alt0 alt1 alt2 alt3 ? gpio[1] etc[1] sout_2 f[1] eirq[1] siul etimer_0 dspi_2 fccu siul i/o i/o o o i slow medium 52 74 90 a[2] (8) pcr[2] alt0 alt1 alt2 alt3 ? ? ? gpio[2] etc[2] cs3 ? sin_2 abs[0] eirq[2] siul etimer_0 dspi_4 ? dspi_2 mc_rgm siul i/o i/o o ? i i i slow medium 57 84 102
package pinouts and signal descriptions spc56xp54x, spc56xp60x 34/104 doc id 18340 rev 3 a[3] (8) pcr[3] alt0 alt1 alt2 alt3 ? ? gpio[3] etc[3] cs0_2 ? abs[1] eirq[3] siul etimer_0 dspi_2 ? mc_rgm siul i/o i/o i/o ? i i slow medium 64 92 116 a[4] (8) pcr[4] alt0 alt1 alt2 alt3 ? ? gpio[4] etc[0] cs1_2 etc[4] fab eirq[4] siul etimer_1 dspi_2 etimer_0 mc_rgm siul i/o i/o o i/o i i slow medium 75 108 132 a[5] pcr[5] alt0 alt1 alt2 alt3 ? gpio[5] cs0_1 etc[5] cs7_0 eirq[5] siul dspi_1 etimer_1 dspi_0 siul i/o i/o i/o o i slow medium 8 14 22 a[6] pcr[6] alt0 alt1 alt2 alt3 ? gpio[6] sck_1 cs2_4 ? eirq[6] siul dspi_1 dspi_4 ? siul i/o i/o i/o ? i slowmedium222 a[7] pcr[7] alt0 alt1 alt2 alt3 ? gpio[7] sout_1 cs1_4 ? eirq[7] siul dspi_1 dspi_4 ? siul i/o o i/o ? i slow medium 4 10 18 a[8] pcr[8] alt0 alt1 alt2 alt3 ? ? gpio[8] ? cs0_4 ? sin_1 eirq[8] siul ? dspi_4 ? dspi_1 siul i/o ? i/o ? i i slow medium 6 12 20 a[9] pcr[9] alt0 alt1 alt2 alt3 ? gpio[9] cs1_2 ? ? sin_4 siul dspi_2 ? ? dspi_4 i/o o ? ? i slow medium 94 134 158 table 7. pin muxing (1) (continued) port pin pcr register alternate function (2),(3) functions peripheral (4) i/o direction (5) pad speed (6) pin src = 0 src = 1 lqfp 100 lqfp 144 lqfp 176 (7)
spc56xp54x, spc56xp60x package pinouts and signal descriptions doc id 18340 rev 3 35/104 a[10] pcr[10] alt0 alt1 alt2 alt3 ? gpio[10] cs0_2 ? ? eirq[9] siul dspi_2 ? ? siul i/o i/o ? ? i slow medium 81 118 142 a[11] pcr[11] alt0 alt1 alt2 alt3 ? gpio[11] sck_2 ? ? eirq[10] siul dspi_2 ? ? siul i/o i/o ? ? i slow medium 82 120 144 a[12] pcr[12] alt0 alt1 alt2 alt3 ? gpio[12] sout_2 ? ? eirq[11] siul dspi_2 ? ? siul i/o o ? ? i slow medium 83 122 146 a[13] pcr[13] alt0 alt1 alt2 alt3 ? ? gpio[13] cs4_1 ? ? sin_2 eirq[12] siul dspi_1 ? ? dspi_2 siul i/o ? ? ? i i slow medium 95 136 160 a[14] pcr[14] alt0 alt1 alt2 alt3 ? gpio[14] txd etc[4] cs5_1 eirq[13] siul safety port etimer_1 dspi_1 siul i/o o i/o o i slow medium 99 143 175 a[15] pcr[15] alt0 alt1 alt2 alt3 ? ? gpio[15] cs6_1 etc[5] ? rxd eirq[14] siul dspi_1 etimer_1 ? safety port siul i/o o i/o ? i i slow medium 100 144 176 port b b[0] pcr[16] alt0 alt1 alt2 alt3 ? gpio[16] txd etc[2] debug[0] eirq[15] siul flexcan_0 etimer_1 sscm siul i/o o i/o ? i slow medium 76 109 133 table 7. pin muxing (1) (continued) port pin pcr register alternate function (2),(3) functions peripheral (4) i/o direction (5) pad speed (6) pin src = 0 src = 1 lqfp 100 lqfp 144 lqfp 176 (7)
package pinouts and signal descriptions spc56xp54x, spc56xp60x 36/104 doc id 18340 rev 3 b[1] pcr[17] alt0 alt1 alt2 alt3 ? ? gpio[17] cs7_1 etc[3] debug[1] rxd eirq[16] siul dspi_1 etimer_1 sscm flexcan_0 siul i/o o i/o ? i i slow medium 77 110 134 b[2] pcr[18] alt0 alt1 alt2 alt3 ? gpio[18] txd sout_4 debug[2] eirq[17] siul linflex_0 dspi_4 sscm siul i/o o i/o ? i slow medium 79 114 138 b[3] pcr[19] alt0 alt1 alt2 alt3 ? gpio[19] ? sck_4 debug[3] rxd siul ? dspi_4 sscm linflex_0 i/o ? i/o ? i slow medium 80 116 140 b[6] pcr[22] alt0 alt1 alt2 alt3 ? gpio[22] clk_out cs2_2 clk_out_div256 eirq[18] siul mc_cgl dspi_2 mc_cgl siul i/o o o o i slow medium 96 138 162 b[7] pcr[23] alt0 alt1 alt2 alt3 ? ? gpio[23] ? ? ? an[0] rxd siul ? ? ? adc_0 linflex_0 input only ? ? 29 43 51 b[8] pcr[24] alt0 alt1 alt2 alt3 ? ? gpio[24] ? ? ? an[1] etc[5] siul ? ? ? adc_0 etimer_0 input only ? ? 31 47 55 b[9] pcr[25] alt0 alt1 alt2 alt3 ? gpio[25] ? ? ? an[11] siul ? ? ? adc_0 input only ? ? 35 52 60 table 7. pin muxing (1) (continued) port pin pcr register alternate function (2),(3) functions peripheral (4) i/o direction (5) pad speed (6) pin src = 0 src = 1 lqfp 100 lqfp 144 lqfp 176 (7)
spc56xp54x, spc56xp60x package pinouts and signal descriptions doc id 18340 rev 3 37/104 b[10] pcr[26] alt0 alt1 alt2 alt3 ? gpio[26] ? ? ? an[12] siul ? ? ? adc_0 input only ? ? 36 53 61 b[11] pcr[27] alt0 alt1 alt2 alt3 ? gpio[27] ? ? ? an[13] siul ? ? ? adc_0 input only ? ? 37 54 62 b[12] pcr[28] alt0 alt1 alt2 alt3 ? gpio[28] ? ? ? an[14] siul ? ? ? adc_0 input only ? ? 38 55 63 b[13] pcr[29] alt0 alt1 alt2 alt3 ? ? gpio[29] ? ? ? an[16] rxd siul ? ? ? adc_0 linflex_1 input only ? ? 42 60 68 b[14] pcr[30] alt0 alt1 alt2 alt3 ? ? ? gpio[30] ? ? ? an[17] etc[4] eirq[19] siul ? ? ? adc_0 etimer_0 siul input only ? ? 44 64 76 b[15] pcr[31] alt0 alt1 alt2 alt3 ? ? gpio[31] ? ? ? an[18] eirq[20] siul ? ? ? adc_0 siul input only ? ? 43 62 70 port c c[0] pcr[32] alt0 alt1 alt2 alt3 ? gpio[32] ? ? ? an[19] siul ? ? ? adc_0 input only ? ? 45 66 78 table 7. pin muxing (1) (continued) port pin pcr register alternate function (2),(3) functions peripheral (4) i/o direction (5) pad speed (6) pin src = 0 src = 1 lqfp 100 lqfp 144 lqfp 176 (7)
package pinouts and signal descriptions spc56xp54x, spc56xp60x 38/104 doc id 18340 rev 3 c[1] pcr[33] alt0 alt1 alt2 alt3 ? gpio[33] ? ? ? an[2] siul ? ? ? adc_0 input only ? ? 28 41 49 c[2] pcr[34] alt0 alt1 alt2 alt3 ? gpio[34] ? ? ? an[3] siul ? ? ? adc_0 input only ? ? 30 45 53 c[3] pcr[35] alt0 alt1 alt2 alt3 ? gpio[35] cs1_0 etc[4] txd eirq[21] siul dspi_0 etimer_1 linflex_1 siul i/o o i/o o i slow medium 10 16 24 c[4] pcr[36] alt0 alt1 alt2 alt3 ? gpio[36] cs0_0 ? debug[4] eirq[22] siul dspi_0 ? sscm siul i/o i/o ? ? i slow medium 5 11 19 c[5] pcr[37] alt0 alt1 alt2 alt3 ? gpio[37] sck_0 sck_4 debug[5] eirq[23] siul dspi_0 dspi_4 sscm siul i/o i/o i/o ? i slow medium 7 13 21 c[6] pcr[38] alt0 alt1 alt2 alt3 ? gpio[38] sout_0 ? debug[6] eirq[24] siul dspi_0 ? sscm siul i/o o ? ? i slow medium 98 142 174 c[7] pcr[39] alt0 alt1 alt2 alt3 ? ? gpio[39] ? ? debug[7] sin_0 sin_4 siul ? ? sscm dspi_0 dspi_4 i/o ? ? ? i i slow medium 9 15 23 c[8] pcr[40] alt0 alt1 alt2 alt3 gpio[40] cs1_1 cs1_4 cs6_0 siul dspi_1 dspi_4 dspi_0 i/o o o o slow medium 91 130 154 table 7. pin muxing (1) (continued) port pin pcr register alternate function (2),(3) functions peripheral (4) i/o direction (5) pad speed (6) pin src = 0 src = 1 lqfp 100 lqfp 144 lqfp 176 (7)
spc56xp54x, spc56xp60x package pinouts and signal descriptions doc id 18340 rev 3 39/104 c[9] pcr[41] alt0 alt1 alt2 alt3 gpio[41] cs3_2 cs0_4 ? siul dspi_2 dspi_4 ? i/o o i/o ? slow medium 84 123 147 c[10] pcr[42] alt0 alt1 alt2 alt3 gpio[42] cs2_2 cs2_4 ? siul dspi_2 dspi_4 ? i/o o o ? slow medium 78 111 135 c[11] pcr[43] alt0 alt1 alt2 alt3 gpio[43] etc[4] cs2_2 cs0_3 siul etimer_0 dspi_2 dspi_3 i/o i/o o i/o slow medium 55 80 96 c[12] pcr[44] alt0 alt1 alt2 alt3 gpio[44] etc[5] cs3_2 cs1_3 siul etimer_0 dspi_2 dspi_3 i/o i/o o o slow medium 56 82 100 c[13] pcr[45] alt0 alt1 alt2 alt3 ? ? gpio[45] etc[1] ? ? ext_in rxd siul etimer_1 ? ? ctu_0 flexcan_1 i/o i/o ? ? i i slow medium 71 101 125 c[14] pcr[46] alt0 alt1 alt2 alt3 gpio[46] etc[2] ext_tgr txd siul etimer_1 ctu_0 flexcan_1 i/o i/o o o slow medium 72 103 127 c[15] pcr[47] alt0 alt1 alt2 alt3 ? gpio[47] ca_tr_en etc[0] ? ext_in siul flexray_0 etimer_1 ? ctu_0 i/o o i/o ? i slow symmet- ric 85 124 148 port d d[0] pcr[48] alt0 alt1 alt2 alt3 gpio[48] ca_tx etc[1] ? siul flexray_0 etimer_1 ? i/o o i/o ? slow symmet- ric 86 125 149 table 7. pin muxing (1) (continued) port pin pcr register alternate function (2),(3) functions peripheral (4) i/o direction (5) pad speed (6) pin src = 0 src = 1 lqfp 100 lqfp 144 lqfp 176 (7)
package pinouts and signal descriptions spc56xp54x, spc56xp60x 40/104 doc id 18340 rev 3 d[1] pcr[49] alt0 alt1 alt2 alt3 ? gpio[49] cs4_1 etc[2] ext_trg ca_rx siul dspi_1 etimer_1 ctu_0 flexray_0 i/o o i/o o i slowmedium333 d[2] pcr[50] alt0 alt1 alt2 alt3 ? gpio[50] cs5_1 etc[3] ? cb_rx siul dspi_1 etimer_1 ? flexray_0 i/o o i/o ? i slow medium 97 140 168 d[3] pcr[51] alt0 alt1 alt2 alt3 gpio[51] cb_tx etc[4] ? siul flexray_0 etimer_1 ? i/o o i/o ? slow symmet- ric 89 128 152 d[4] pcr[52] alt0 alt1 alt2 alt3 gpio[52] cb_tr_en etc[5] ? siul flexray_0 etimer_1 ? i/o o i/o ? slow symmet- ric 90 129 153 d[5] pcr[53] alt0 alt1 alt2 alt3 gpio[53] cs3_0 ? sout_3 siul dspi_0 ? dspi_3 i/o o ? o slow medium 22 33 41 d[6] pcr[54] alt0 alt1 alt2 alt3 gpio[54] cs2_0 sck_3 sout_4 siul dspi_0 dspi_3 dspi_4 i/o o i/o o slow medium 23 34 42 d[7] pcr[55] alt0 alt1 alt2 alt3 ? gpio[55] cs3_1 ? cs4_0 sin_3 siul dspi_1 ? dspi_0 dspi_3 i/o o ? o i slow medium 26 37 45 d[8] pcr[56] alt0 alt1 alt2 alt3 gpio[56] cs2_1 rdy cs5_0 siul dspi_1 nexus_0 dspi_0 i/o o o o slow medium 21 32 40 d[9] pcr[57] alt0 alt1 alt2 alt3 gpio[57] ? txd cs6_1 siul ? linflex_1 dspi_1 i/o ? o o slow medium 15 26 34 table 7. pin muxing (1) (continued) port pin pcr register alternate function (2),(3) functions peripheral (4) i/o direction (5) pad speed (6) pin src = 0 src = 1 lqfp 100 lqfp 144 lqfp 176 (7)
spc56xp54x, spc56xp60x package pinouts and signal descriptions doc id 18340 rev 3 41/104 d[10] pcr[58] alt0 alt1 alt2 alt3 gpio[58] ? cs0_3 ? siul ? dspi_3 ? i/o ? i/o ? slow medium 53 76 92 d[11] pcr[59] alt0 alt1 alt2 alt3 gpio[59] ? cs1_3 sck_3 siul ? dspi_3 dspi_3 i/o ? o i/o slow medium 54 78 94 d[12] pcr[60] alt0 alt1 alt2 alt3 ? gpio[60] ? ? ds7_1 rxd siul ? ? dspi_1 linflex_1 i/o ? ? o i slow medium 70 99 123 d[13] pcr[61] alt0 alt1 alt2 alt3 gpio[61] ? cs2_3 sout_3 siul ? dspi_3 dspi_3 i/o ? o o slow medium 67 95 119 d[14] pcr[62] alt0 alt1 alt2 alt3 ? gpio[62] ? cs3_3 ? sin_3 siul ? dspi_3 ? dspi_3 i/o ? o ? i slow medium 73 105 129 d[15] pcr[63] alt0 alt1 alt2 alt3 ? gpio[63] ? ? ? an[20] siul ? ? ? adc_0 input only ? ? 41 58 66 port e e[0] pcr[64] alt0 alt1 alt2 alt3 ? gpio[64] ? ? ? an[21] siul ? ? ? adc_0 input only ? ? 46 68 80 e[1] pcr[65] alt0 alt1 alt2 alt3 ? gpio[65] ? ? ? an[4] siul ? ? ? adc_0 input only ? ? 27 39 47 table 7. pin muxing (1) (continued) port pin pcr register alternate function (2),(3) functions peripheral (4) i/o direction (5) pad speed (6) pin src = 0 src = 1 lqfp 100 lqfp 144 lqfp 176 (7)
package pinouts and signal descriptions spc56xp54x, spc56xp60x 42/104 doc id 18340 rev 3 e[2] pcr[66] alt0 alt1 alt2 alt3 ? gpio[66] ? ? ? an[5] siul ? ? ? adc_0 input only ? ? 32 49 57 e[3] pcr[67] alt0 alt1 alt2 alt3 ? gpio[67] ? ? ? an[6] siul ? ? ? adc_0 input only ? ? ? 40 48 e[4] pcr[68] alt0 alt1 alt2 alt3 ? gpio[68] ? ? ? an[7] siul ? ? ? adc_0 input only ? ? ? 42 50 e[5] pcr[69] alt0 alt1 alt2 alt3 ? gpio[69] ? ? ? an[8] siul ? ? ? adc_0 input only ? ? ? 44 52 e[6] pcr[70] alt0 alt1 alt2 alt3 ? gpio[70] ? ? ? an[9] siul ? ? ? adc_0 input only ? ? ? 46 54 e[7] pcr[71] alt0 alt1 alt2 alt3 ? gpio[71] ? ? ? an[10] siul ? ? ? adc_0 input only ? ? ? 48 56 e[8] pcr[72] alt0 alt1 alt2 alt3 ? gpio[72] ? ? ? an[22] siul ? ? ? adc_0 input only ? ? ? 59 67 e[9] pcr[73] alt0 alt1 alt2 alt3 ? gpio[73] ? ? ? an[23] siul ? ? ? adc_0 input only ? ? ? 61 69 table 7. pin muxing (1) (continued) port pin pcr register alternate function (2),(3) functions peripheral (4) i/o direction (5) pad speed (6) pin src = 0 src = 1 lqfp 100 lqfp 144 lqfp 176 (7)
spc56xp54x, spc56xp60x package pinouts and signal descriptions doc id 18340 rev 3 43/104 e[10] pcr[74] alt0 alt1 alt2 alt3 ? gpio[74] ? ? ? an[24] siul ? ? ? adc_0 input only ? ? ? 63 75 e[11] pcr[75] alt0 alt1 alt2 alt3 ? gpio[75] ? ? ? an[25] siul ? ? ? adc_0 input only ? ? ? 65 77 e[12] pcr[76] alt0 alt1 alt2 alt3 ? gpio[76] ? ? ? an[26] siul ? ? ? adc_0 input only ? ? ? 67 79 e[13] pcr[77] alt0 alt1 alt2 alt3 ? gpio[77] sck_3 ? ? eirq[25] siul dspi_3 ? ? siul i/o i/o ? ? i slow medium ? 117 141 e[14] pcr[78] alt0 alt1 alt2 alt3 ? gpio[78] sout_3 ? ? eirq[26] siul dspi_3 ? ? siul i/o o ? ? i slow medium ? 119 143 e[15] pcr[79] alt0 alt1 alt2 alt3 ? ? gpio[79] ? ? ? sin_3 eirq[27] siul ? ? ? dspi_3 siul i/o ? ? ? i i slow medium ? 121 145 port f f[0] pcr[80] alt0 alt1 alt2 alt3 ? gpio[80] dbg_0 cs3_3 ? eirq[28] siul flexray_0 dspi_3 ? siul i/o o o ? i slow medium ? 133 157 table 7. pin muxing (1) (continued) port pin pcr register alternate function (2),(3) functions peripheral (4) i/o direction (5) pad speed (6) pin src = 0 src = 1 lqfp 100 lqfp 144 lqfp 176 (7)
package pinouts and signal descriptions spc56xp54x, spc56xp60x 44/104 doc id 18340 rev 3 f[1] pcr[81] alt0 alt1 alt2 alt3 ? gpio[81] dbg_1 cs2_3 ? eirq[29] siul flexray_0 dspi_3 ? siul i/o o o ? i slow medium ? 135 159 f[2] pcr[82] alt0 alt1 alt2 alt3 gpio[82] dbg_2 cs1_3 ? siul flexray_0 dspi_3 ? i/o o o ? slow medium ? 137 161 f[3] pcr[83] alt0 alt1 alt2 alt3 gpio[83] dbg_3 cs0_3 ? siul flexray_0 dspi_3 ? i/o o i/o ? slow medium ? 139 167 f[4] pcr[84] alt0 alt1 alt2 alt3 ? ? mdo[3] ? ? ? nexus_0 ? ? ? o ? slow fast ? 4 4 f[5] pcr[85] alt0 alt1 alt2 alt3 ? ? mdo[2] ? ? ? nexus_0 ? ? ? o ? slow fast ? 5 13 f[6] pcr[86] alt0 alt1 alt2 alt3 gpio[86] ? mdo[1] ? siul ? nexus_0 ? i/o ? o ? slow fast ? 8 16 f[7] pcr[87] alt0 alt1 alt2 alt3 gpio[87] ? mcko ? siul ? nexus_0 ? i/o ? o ? slow fast ? 19 27 f[8] pcr[88] alt0 alt1 alt2 alt3 gpio[88] ? mseo1 ? siul ? nexus_0 ? i/o ? o ? slow fast ? 20 28 f[9] pcr[89] alt0 alt1 alt2 alt3 gpio[89] ? mseo0 ? siul ? nexus_0 ? i/o ? o ? slow fast ? 23 31 table 7. pin muxing (1) (continued) port pin pcr register alternate function (2),(3) functions peripheral (4) i/o direction (5) pad speed (6) pin src = 0 src = 1 lqfp 100 lqfp 144 lqfp 176 (7)
spc56xp54x, spc56xp60x package pinouts and signal descriptions doc id 18340 rev 3 45/104 f[10] pcr[90] alt0 alt1 alt2 alt3 gpio[90] ? evto ? siul ? nexus_0 ? i/o ? o ? slow fast ? 24 32 f[11] pcr[91] alt0 alt1 alt2 alt3 gpio[91] evti ? ? siul nexus_0 ? ? i/o i ? ? slow medium ? 25 33 f[12] pcr[92] alt0 alt1 alt2 alt3 gpio[92] etc[3] ? ? siul etimer_1 ? ? i/o i/o ? ? slow medium ? 106 130 f[13] pcr[93] alt0 alt1 alt2 alt3 gpio[93] etc[4] ? ? siul etimer_1 ? ? i/o i/o ? ? slow medium ? 112 136 f[14] pcr[94] alt0 alt1 alt2 alt3 gpio[94] txd ? ? siul linflex_1 ? ? i/o o ? ? slow medium ? 115 139 f[15] pcr[95] alt0 alt1 alt2 alt3 ? gpio[95] ? ? ? rxd siul ? ? ? linflex_1 i/o ? ? ? i slow medium ? 113 137 port g g[0] pcr[96] alt0 alt1 alt2 alt3 ? gpio[96] f[0] ? ? eirq[30] siul fccu ? ? siul i/o o ? ? i slow medium ? 38 46 g[1] pcr[97] alt0 alt1 alt2 alt3 ? gpio[97] f[1] ? ? eirq[31] siul fccu ? ? siul i/o o ? ? i slow medium ? 141 173 table 7. pin muxing (1) (continued) port pin pcr register alternate function (2),(3) functions peripheral (4) i/o direction (5) pad speed (6) pin src = 0 src = 1 lqfp 100 lqfp 144 lqfp 176 (7)
package pinouts and signal descriptions spc56xp54x, spc56xp60x 46/104 doc id 18340 rev 3 g[2] pcr[98] alt0 alt1 alt2 alt3 ? gpio[98] ? ? ? sin_4 siul ? ? ? dspi_4 i/o ? ? ? i slow medium ? 102 126 g[3] pcr[99] alt0 alt1 alt2 alt3 gpio[99] ? sout_4 ? siul ? dspi_4 ? i/o ? o ? slow medium ? 104 128 g[4] pcr[100] alt0 alt1 alt2 alt3 gpio[100] ? sck_4 ? siul ? dspi_4 ? i/o ? i/o ? slow medium ? 100 124 g[5] pcr[101] alt0 alt1 alt2 alt3 gpio[101] ? cs0_4 ? siul ? dspi_4 ? i/o ? i/o ? slow medium ? 85 103 g[6] pcr[102] alt0 alt1 alt2 alt3 gpio[102] ? cs1_4 ? siul ? dspi_4 ? i/o ? o ? slow medium ? 98 122 g[7] pcr[103] alt0 alt1 alt2 alt3 gpio[103] ? cs2_4 ? siul ? dspi_4 ? i/o ? o ? slow medium ? 83 101 g[8] pcr[104] alt0 alt1 alt2 alt3 ? gpio[104] ? cs3_4 ? siul ? dspi_4 ? i/o ? o ? slow medium ? 81 97 g[9] pcr[105] alt0 alt1 alt2 alt3 ? gpio[105] ? ? ? rxd siul ? ? ? flexcan_1 i/o ? ? ? i slow medium ? 79 95 table 7. pin muxing (1) (continued) port pin pcr register alternate function (2),(3) functions peripheral (4) i/o direction (5) pad speed (6) pin src = 0 src = 1 lqfp 100 lqfp 144 lqfp 176 (7)
spc56xp54x, spc56xp60x package pinouts and signal descriptions doc id 18340 rev 3 47/104 g[10] pcr[106] alt0 alt1 alt2 alt3 gpio[106] ? txd ? siul ? flexcan_1 ? i/o ? o ? slow medium ? 77 93 g[11] pcr[107] alt0 alt1 alt2 alt3 gpio[107] ? ? ? siul ? ? ? i/o ? ? ? slow medium ? 75 91 1. this table concerns full-featured ve rsion. please refer to ?spc56xp54/60 devi ce configuration difference? table for difference between full-featured, and airbag configuration. 2. alt0 is the primar y (default) function for each port after reset. 3. alternate functions are chosen by setting the values of the pcr[pa] bitfields inside the siu module. pcr[pa] = 00 ? alt0; pcr[pa] = 01 ? alt1; pcr[pa] = 10 ? alt2; pcr[pa] = 11 ? alt3. this is intended to select the output functions; to use one of the input-only functions, the pcr[ibe] bit must be written to ?1?, regardless of the values selected in the pcr[pa] bitfields. for this reason, the val ue corresponding to an input onl y function is reported as ???. 4. module included on the mcu. 5. multiple inputs are routed to all respecti ve modules internally. the input of some modules must be configured by setting the values of the psmi[padsel x ] bitfields inside the siul module. 6. programmable via the src (slew rate control) bits in the respective pad configuration register. 7. lqfp176 available only as development package. 8. weak pull down during reset. table 7. pin muxing (1) (continued) port pin pcr register alternate function (2),(3) functions peripheral (4) i/o direction (5) pad speed (6) pin src = 0 src = 1 lqfp 100 lqfp 144 lqfp 176 (7)
electrical characteristics spc56xp54x, spc56xp60x 48/104 doc id 18340 rev 3 3 electrical characteristics 3.1 introduction this section contains electrical characteristics of the device as well as temperature and power considerations. this product contains devices to protect the inputs against damage due to high static voltages. however, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. to enhance reliability, unused inputs can be driven to an appr opriate logic voltage level (v dd or v ss ). this can be done by the internal pull-up or pull-down, which is provided by the product for most general purpose pins. the parameters listed in the following tables represent the characteristics of the device and its demands on the system. in the tables where the device logic provides signals with their respective timing characteristics, the symbol ?cc? for controller characteristics is included in the symbol column. in the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol ?sr? for system requirement is included in the symbol column. caution: all of the following parameter values can vary depending on the application and must be confirmed during silicon validation, silicon characteriza tion or silicon reliability trial. 3.2 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding, the classifications listed in ta b l e 8 are used and the parameters are tagged accordingly in the tables where appropriate. note: the classification is shown in the column labeled ?c? in the parameter tables where appropriate. table 8. parameter classifications classification tag tag description p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design c haracterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwi se noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations.
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 49/104 3.3 absolute maximum ratings table 9. absolute maximum ratings (1) symbol parameter conditions min max (2) unit v ss_hv sr digital ground ? 0 0 v v dd_hv_iox (3) sr 3.3 v / 5.0 v input/output supply voltage with respect to ground (v ss_hv ) ??0.36.0v v ss_hv_iox sr input/output ground voltage with respect to ground (v ss_hv ) ??0.10.1v v dd_hv_fl sr 3.3 v / 5.0 v code and data flash memory supply voltage with respect to ground (v ss_hv ) ??0.36.0 v relative to v dd_hv_iox ?0.3 v dd_hv_iox + 0.3 v ss_hv_fl sr code and data flash memory ground with respect to ground (v ss_hv ) ??0.10.1v v dd_hv_osc sr 3.3 v / 5.0 v crystal oscillator amplifier supply voltage with respect to ground (v ss_hv ) ??0.36.0 v relative to v dd_hv_iox ?0.3 v dd_hv_iox + 0.3 v ss_hv_osc sr 3.3 v / 5.0 v crystal oscillator amplifier reference voltage with respect to ground (v ss_hv ) ??0.10.1v v dd_hv_reg sr 3.3 v / 5.0 v voltage regulator supply voltage with respect to ground (v ss_hv ) ? ? 0.3 6.0 v relative to v dd_hv_iox ? 0.3 v dd_hv_iox + 0.3 v dd_hv_ad sr 3.3 v / 5.0 v adc supply and high reference voltage with respect to ground (v ss_hv ) v dd_hv_reg < 2.7 v ? 0.3 v dd_hv_reg + 0.3 v v dd_hv_reg > 2.7 v ? 0.3 6.0 v ss_hv_ad sr adc ground and low reference voltage with respect to ground (v ss_hv ) ??0.10.1v tv dd (4) sr slope characteristics on all v dd during power up (5) with respect to ground (v ss_hv ) ?0.25250v/ms v in sr voltage on any pin with respect to ground (v ss_hv_iox ) with respect to ground (v ss_hv ) ??0.36.0 v relative to v dd_hv_iox ?0.3 v dd_hv_iox + 0.3 v inan sr analog input voltage v dd_hv_reg < 2.7 v v ss_hv_ad ??? 0.3 v dd_hv_ad + 0.3 v v dd_hv_reg > 2.7 v v ss_hv_ad v dd_hv_ad v i injpad sr injected input current on any pin during overload condition ? ?10 10 ma
electrical characteristics spc56xp54x, spc56xp60x 50/104 doc id 18340 rev 3 figure 5 shows the constraints of the different power supplies. figure 5. power supplies constraints the spc56xp54/60 supply architecture provides an adc supply that is managed independently of standard v dd_hv supply. figure 6 shows the constraints of the adc power supply. i injsum sr absolute sum of all injected input currents during overload condition ? ?50 50 ma i vdd_lv sr low voltage static current sink through v dd_lv ??155ma t stg sr storage temperature ? ?55 150 c t j sr junction temperature under bias ? ?40 150 c 1. functional operating conditions are given in the dc electrical characteristics. abso lute maximum ratings are stress ratings only, and functional operation at the maxima is not guarant eed. stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2. absolute maximum voltages are currently maximum burn-in vo ltages. absolute maximum specif ications for device stress have not yet been determined. 3. the difference between each couple of voltage supplies must be less than 300 mv, |v dd_hv_ioy ? v dd_hv_iox | < 300 mv. 4. ensure a monotonic supply ramp starting at ground level 5. guaranteed by device validation table 9. absolute maximum ratings (1) (continued) symbol parameter conditions min max (2) unit vdd_hv_xxx vdd_hv_iox -0.3v 6.0v -0.3v 6.0v
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 51/104 figure 6. independent adc supply (d) 3.4 recommended operating conditions d. device design targets the removal of this condition s. to be confirmed by des ign during device validation. vdd_hv_ad 6.0v vdd_hv_reg -0.3v 2.7v -0.3v 6.0v table 10. recommended operating conditions (5.0 v) symbol parameter conditions min max (1) unit v ss_hv sr digital ground ? 0 0 v v dd_hv_iox (2) sr 5.0 v input/output supply voltage ?4.5 5.5v v ss_hv_iox sr input/output ground voltage ? 0 0 v v dd_hv_fl sr 5.0 v code and data flash memory supply voltage ?4.5 5.5 v relative to v dd_hv_iox v dd_hv_iox ? 0.1 v dd_hv_iox +0.1 v ss_hv_fl sr code and data flash memory ground ?0 0v v dd_hv_osc sr 5.0 v crystal oscillator amplifier supply voltage ?4.5 5.5 v relative to v dd_hv_iox v dd_hv_iox ? 0.1 v dd_hv_iox +0.1 v ss_hv_osc sr 5.0 v crystal oscillator amplifier reference voltage ?0 0v
electrical characteristics spc56xp54x, spc56xp60x 52/104 doc id 18340 rev 3 v dd_hv_reg sr 5.0 v voltage regulator supply voltage ?4.5 5.5 v relative to v dd_hv_iox v dd_hv_iox ? 0.1 v dd_hv_iox +0.1 v dd_hv_ad sr 5.0 v adc supply and high reference voltage ?4.5 5.5 v relative to v dd_hv_reg v dd_hv_reg ? 0.1 ? v ss_hv_ad sr adc ground and low reference voltage ?0 0v v dd_lv_regcor (3),(4) sr internal supply voltage ? ? ? v v ss_lv_regcor (3) sr internal reference voltage ? 0 0 v v dd_lv_corx (3),(4) sr internal supply voltage ? ? ? v v ss_lv_corx (3) sr internal reference voltage ? 0 0 v t a sr ambient temperature under bias ? ?40 125 c 1. parametric figures can be out of specification when voltage drops below 4.5 v, however, guarant eeing the full functionality. in particular, adc electrical c haracteristics and i/os dc electrical specification may not be guaranteed. 2. the difference between each couple of voltage supplies must be less than 100 mv, |v dd_hv_ioy ? v dd_hv_iox | < 100 mv. 3. to be connected to emitter of external npn. low voltage supplies are not under user cont rol?these are produced by an on-chip voltage regulator?but for the device to function properly the low voltage grounds (v ss_lv_xxx ) must be shorted to high voltage grounds (v ss_hv_xxx ) and the low voltage supply pins (v dd_lv_xxx ) must be connected to the external ballast emitter. 4. the low voltage supplies (v dd_lv_xxx ) are not all independent. v dd_lv_cor1 and v dd_lv_cor2 are shorted internally via double bonding con nections with lines t hat provide the low voltage supply to the data flash memory module. similarly, v ss_lv_cor1 and v ss_lv_cor2 are internally shorted. v dd_lv_regcor and v dd_lv_regcorx are physically shorted internally, as are v ss_lv_regcor and v ss_lv_corx . table 10. recommended operating conditions (5.0 v) (continued) symbol parameter conditions min max (1) unit table 11. recommended operating conditions (3.3 v) symbol parameter conditions min max (1) unit v ss_hv sr digital ground ? 0 0 v v dd_hv_iox (2) sr 3.3 v input/output supply voltage ?3.0 3.6v v ss_hv_iox sr input/output ground voltage ? 0 0 v v dd_hv_fl sr 3.3 v code and data flash memory supply voltage ?3.0 3.6 v relative to v dd_hv_iox v dd_hv_iox ? 0.1 v dd_hv_iox +0.1 v ss_hv_fl sr code and data flash memory ground ?0 0v v dd_hv_osc sr 3.3 v crystal oscillator amplifier supply voltage ?3.0 3.6 v relative to v dd_hv_iox v dd_hv_iox ? 0.1 v dd_hv_iox +0.1 v ss_hv_osc sr 3.3 v crystal oscillator amplifier reference voltage ?0 0v
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 53/104 figure 7 shows the constraints of the different power supplies. v dd_hv_reg sr 3.3 v voltage regulator supply voltage ?3.0 3.6 v relative to v dd_hv_iox v dd_hv_iox ? 0.1 v dd_hv_iox +0.1 v dd_hv_ad sr 3.3 v adc supply and high reference voltage ?3.0 5.5 v relative to v dd_hv_reg v dd_hv_reg ? 0.1 5.5 v ss_hv_ad sr adc ground and low reference voltage ?0 0v v dd_lv_regcor (3),(4) sr internal supply voltage ? ? ? v v ss_lv_regcor (3) sr internal reference voltage ? 0 0 v v dd_lv_corx (3),(4) sr internal supply voltage ? ? ? v v ss_lv_corx (3) sr internal reference voltage ? 0 0 v t a sr ambient temperature under bias ? ?40 125 c 1. parametric figures can be out of specification when voltage drops below 4.5 v, however, guarant eeing the full functionality. in particular, adc electrical c haracteristics and i/os dc electrical specification may not be guaranteed. 2. the difference between each couple of voltage supplies must be less than 100 mv, |v dd_hv_ioy ? v dd_hv_iox | < 100 mv. 3. to be connected to emitter of external npn. low voltage supplies are not under user cont rol?these are produced by an on-chip voltage regulator?but for the device to function properly the low voltage grounds (v ss_lv_xxx ) must be shorted to high voltage grounds (v ss_hv_xxx ) and the low voltage supply pins (v dd_lv_xxx ) must be connected to the external ballast emitter. 4. the low voltage supplies (v dd_lv_xxx ) are not all independent. v dd_lv_cor1 and v dd_lv_cor2 are shorted internally via double bonding con nections with lines t hat provide the low voltage supply to the data flash memory module. similarly, v ss_lv_cor1 and v ss_lv_cor2 are internally shorted. v dd_lv_regcor and v dd_lv_regcorx are physically shorted internally, as are v ss_lv_regcor and v ss_lv_corx . table 11. recommended operating conditions (3.3 v) (continued) symbol parameter conditions min max (1) unit
electrical characteristics spc56xp54x, spc56xp60x 54/104 doc id 18340 rev 3 figure 7. power supplies constraints (e) the spc56xp54/60 supply architecture provides an adc supply that is managed independently of standard v dd_hv supply. figure 8 shows the constraints of the adc power supply. e. io ac and dc characteristics ar e guaranteed only in the range 3.0v?3.6v when pad3v5v is low, and in the range 4.5v?5.5v when pad3v5v is high. vdd_hv_xxx vdd_hv_iox 3.2v 5.5v 3.2v 5.5v 3.3v 3.3v
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 55/104 figure 8. independent adc supply 3.5 thermal characteristics 5.5v 3.0v vdd_hv_reg 3.0v 5.5v vdd_hv_ad table 12. thermal characteristics for 144-pin lqfp symbol parameter conditions typical value unit r ? ja d thermal resistance junction-to-ambient, natural convection (1) single layer board?1s 53.4 c/w d four layer board?2s2p 43.9 c/w r ? jb d thermal resistance junction-to-board (2) four layer board?2s2p 29.6 c/w r ? jctop d thermal resistance junction-to-case (top) (3) single layer board?1s 9.3 c/w ? jb d junction-to-board, natural convection (4) operating conditions 29.8 c/w ? jc d junction-to-case, natural convection (5) operating conditions 1.3 c/w 1. junction-to-ambient thermal resistance determined per jedec jesd51-7. th ermal test board meets jedec specification for this package. 2. junction-to-board thermal resistance det ermined per jedec jesd51-8. thermal test board meets jedec specification for the specified package. 3. junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value incl udes the thermal resistance of the interface layer. 4. thermal characterization parameter i ndicating the temperature difference betw een the board and the junction temperature per jedec jesd51-2. when greek letters are not available, t he thermal characteri zation parameter is written as psi-jb. 5. thermal characterization parameter indicating the temperat ure difference between the case and the junction temperature per jedec jesd51-2. when greek letters are not available, t he thermal characteri zation parameter is written as psi-jc.
electrical characteristics spc56xp54x, spc56xp60x 56/104 doc id 18340 rev 3 3.5.1 general notes for sp ecifications at maximum junction temperature an estimation of the chip junction temperature, t j , can be obtained from equation 1 : equation 1 t j = t a + (r ? ja p d ) where: t a = ambient temperature for the package ( o c) r ? ja = junction to ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) the junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. for packages such as the pbga, these values can be different by a factor of two. which value is closer to the application depends on the power dissipated by other components on the board. the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. the value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. when a heat sink is used, the thermal resistance is expressed in equation 2 as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: equation 2 r ? ja = r ? jc + r ? ca where: r ? ja = junction to ambient thermal resistance (c/w) r ? jc = junction to case thermal resistance (c/w) r ? ca = case to ambient thermal resistance (c/w) table 13. thermal characteristics for 100-pin lqfp symbol parameter conditions typical value unit r ? ja d thermal resistance junction-to-ambient, natural convection (1) single layer board?1s 47.3 c/w d four layer board?2s2p 35.6 c/w r ? jb d thermal resistance junction-to-board (2) four layer board?2s2p 19.1 c/w r ? jctop d thermal resistance junction-to-case (top) (3) single layer board?1s 9.1 c/w ? jb d junction-to-board, natural convection (4) operating conditions 19.1 c/w ? jc d junction-to-case, natural convection (5) operating conditions 1.1 c/w 1. junction-to-ambient thermal resistance determined per jedec jesd51-7. th ermal test board meets jedec specification for this package. 2. junction-to-board thermal resistance det ermined per jedec jesd51-8. thermal test board meets jedec specification for the specified package. 3. junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value incl udes the thermal resistance of the interface layer. 4. thermal characterization parameter i ndicating the temperature difference betw een the board and the junction temperature per jedec jesd51-2. when greek letters are not available, t he thermal characteri zation parameter is written as psi-jb. 5. thermal characterization parameter indicating the temperat ure difference between the case and the junction temperature per jedec jesd51-2. when greek letters are not available, t he thermal characteri zation parameter is written as psi-jc.
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 57/104 r ? jc is device related and cannot be influenced by the user. the user controls the thermal environment to change the case to ambient thermal resistance, r ? ca . for instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. to determine the junction temperature of the device in the application when heat sinks are not used, the thermal characterization parameter ( ? jt ) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using equation 3 : equation 3 t j = t t + ( ? jt p d ) where: t t = thermocouple temperature on top of the package (c) ? jt = thermal characterization parameter (c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured per jesd51-2 specification using a 40 gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. references semiconductor equipment and materials international 3081 zanker road san jose, ca 95134 u.s.a. (408) 943-6900 mil-spec and eia/jesd (jedec) specificatio ns are available from global engineering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org. 1. c.e. triplett and b. joiner, an experimental characterization of a 272 pbga within an automotive engine controller module , proceedings of semitherm, san diego, 1998, pp. 47-54. 2. g. kromann, s. shidore, and s. addison, thermal modeling of a pbga for air-cooled applications , electronic packaging and production, pp. 53-58, march 1998. 3. b. joiner and v. adams, measurement and simulation of junction to board thermal resistance and its applic ation in thermal modeling , proceedings of semitherm, san diego, 1999, pp. 212-220.
electrical characteristics spc56xp54x, spc56xp60x 58/104 doc id 18340 rev 3 3.6 electromagnetic interfer ence (emi) characteristics 3.7 electrostatic discharg e (esd) characteristics 3.8 power management el ectrical characteristics 3.8.1 voltage regulator electrical characteristics the internal voltage regulator requires an external npn ballast to be connected as shown in figure 9 . ta bl e 1 6 contains all approved npn ballast components. capacitances should be placed on the board as near as possible to the associated pins. care should also be taken to limit the serial inductance of the v dd_hv_reg , bctrl and v dd_lv_corx pins to less than l reg , see ta b l e 1 7 . note: the voltage regulator output cannot be used to drive external circuits. output pins are used only for decoupling capacitances. v dd_lv_cor must be generated using internal regulator and external npn transistor. it is not possible to provide v dd_lv_cor through external regulator. for the spc56xp54/60 microcontroller, capacitors, wit h total values not below c dec1 , should be placed between v dd_lv_corx /v ss_lv_corx close to external ballast transistor emitter. 4 capacitors, with total values not below c dec2 , should be placed close to microcontroller pins between each v dd_lv_corx /v ss_lv_corx supply pairs and the table 14. emi testing specifications parameter symbol conditions f osc /f bus frequency level (max) unit v re_tem radiated emissions, electric field v dd =5v; t a =25c 150 khz?30 mhz rbw 9 khz, step size 5 khz 30 mhz?1 ghz rbw 120 khz, step size 80 khz 8 mhz crystal 64 mhz bus no pll frequency modulation 150 khz?150 mhz 18 db ? v 150?1000 mhz 12 iec level m ? 8 mhz crystal 64 mhz bus 2% pll frequency modulation 150 khz?150 mhz 18 db ? v 150?1000 mhz 12 iec level m ? table 15. esd ratings (1),(2) symbol parameter conditions value unit v esd(hbm) sr electrostatic discharge (human body model) ? 2000 v v esd(cdm) sr electrostatic discharge (charged device model) ? 750 (corners) v 500 (other) 1. all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. 2. a device will be defined as a failure if after exposure to esd pulses the devic e no longer meets the device specification requirements. complete dc parametric and functional testing shall be performed per applicabl e device specification at room temperature followed by hot temperature, unles s specified otherwise in the device specification
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 59/104 v dd_lv_regcor /v ss_lv_regcor pair . additionally, capacitors with total values not below c dec3 , should be placed between the v dd_hv_reg /v ss_hv_reg pins close to ballast collector. capacitors values have to take into account capacitor accuracy, aging and variation versus temperature. all reported information are valid for voltage and temperature ranges described in recommended operating condition, ta bl e 1 0 and ta bl e 1 1 . figure 9. voltage regulator configuration table 16. approved npn ballast components part manufacturer approved derivatives (1) 1. for automotive applications pleas e check with the appropriate trans istor vendor for automotive grade certification bcp68 on semi bcp68 nxp bcp68-25 infineon bcp68-25 bcx68 infineon bcx68-10;bcx68-16;bcx68-25 bc868 nxp bc868 bc817 infineon bc817-16;bc817-25;bc817su; nxp bc817-16;bc817-25 bcp56 st bcp56-16 infineon bcp56-10;bcp56-16 on semi bcp56-10 nxp bcp56-10;bcp56-16 bctrl vdd_lv_cor c dec3 c dec2 c dec1 vdd_hv_reg bjt (1) spc56xp54/60 1. refer to table 16 .
electrical characteristics spc56xp54x, spc56xp60x 60/104 doc id 18340 rev 3 3.8.2 voltage monitor el ectrical characteristics the device implements a power on reset module to ensure correct power-up initialization, as well as three low voltage detectors to monitor the v dd and the v dd_lv voltage while device is supplied: por monitors v dd during the power-up phase to ensure device is maintained in a safe reset state lvdhv3 monitors v dd to ensure device reset below minimum functional supply lvdhv5 monitors v dd when application uses device in the 5.0v 10% range lvdlvcor monitors low voltage digital power domain table 17. voltage regulator electrical characteristics symbol c parameter conditions value unit min typ max v dd_lv_regcor cc p output voltage under maximum load run supply current configuration post-trimming 1.15 ? 1.32 v c dec1 sr ? external decoupling/stability ceramic capacitor bjt from ta b l e 1 6 . 3 capacitances (i.e. x7r or x8r capacitors) with nominal value of 10 f 19.5 30 ? f bjt bc817, one capacitance of 22 f 14.3 22 f r reg sr ? resulting esr of all three capacitors of c dec1 bjt from ta b l e 1 6 . 3x10 f. absolute maximum value between 100 khz and 10 mhz ??50m ? resulting esr of the unique capacitor c dec1 bjt bc817, 1x 22 f. absolute maximum value between 100 khz and 10 mhz 10 ? 40 m ? c dec2 sr ? external decoupling/stability ceramic capacitor 4 capacitances (i.e. x7r or x8r capacitors) with nominal value of 440 nf 1200 1760 ? nf c dec3 sr ? external decoupling/stability ceramic capacitor on v dd_hv_reg 3 capacitances (i.e. x7r or x8r capacitors) with nominal value of 10 f; c dec3 has to be equal or greater than c dec1 19.5 30 ? f l reg sr ? resulting esl of v dd_hv_reg , bctrl and v dd_lv_corx pins ???15nh
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 61/104 3.9 power up/down sequencing to prevent an overstress event or a malfunction within and outside the device, the spc56xp54/60 implements the following sequence to ensure each module is started only when all conditions for swit ching it on are available: 1. a power_on module working on voltage regulator supply controls the correct start- up of the regulator. this is a key module ensuring safe configuration for all voltage regulator functionality when supply is below 1.5v. associated power_on (or por) signal is active low. ? several low voltage detectors, working on voltage regulator supply monitor the voltage of the critical modules (voltage regulator, i/os, flash memory and low voltage domain). lvds are gated low when power_on is active. ? a power_ok signal is generated when all critical supplies monitored by the lvd are available. this signal is active high and released to all modules including i/os, flash memory and rc16 oscillator neede d during power-up phase and reset phase. when power_ok is low the associated modules are set into a safe state. table 18. low voltage monito r electrical characteristics symbol parameter conditions (1) value unit min max v porh t power-on reset threshold ? 1.5 2.7 v v porup p supply for functional por module t a = 25c 1.0 ? v v reglvdmok_h p regulator low voltage detector high threshold ? ? 2.95 v v reglvdmok_l p regulator low voltage detector low threshold ? 2.6 ? v v fllvdmok_h p flash memory low voltage detector high threshold ? ? 2.95 v v fllvdmok_l p flash memory low voltage detector low threshold ? 2.6 ? v v iolvdmok_h p i/o low voltage detector high threshold ? ? 2.95 v v iolvdmok_l p i/o low voltage detector low threshold ? 2.6 ? v v iolvdm5ok_h p i/o 5v low voltage detector high threshold ? ? 4.4 v v iolvdm5ok_l p i/o 5v low voltage detector low threshold ? 3.8 ? v v mlvddok_h p digital supply low voltage detector high ? ? 1.15 v v mlvddok_l p digital supply low voltage detector low ? 1.08 ? v 1. v dd = 3.3v 10% / 5.0v 10%, t a = ?40 c to t a max , unless otherwise specified
electrical characteristics spc56xp54x, spc56xp60x 62/104 doc id 18340 rev 3 figure 10. power-up typical sequence figure 11. power-down typical sequence vdd_hv_reg 0v 3.3v 0v 3.3v vdd_lv_regcor 0v 1.2v 0v 3.3v power_on lvdm (hv) 0v lvdd (lv) 3.3v 0v power_ok 3.3v rc16mhz oscillator 0v 1.2v p0 p1 0v 1.2v internal reset generation module fsm ~1us v por_up v porh v lvdhv3h v mlvdok_h vdd_hv_reg 0v 3.3v 0v 3.3v vdd_lv_regcor 0v 1.2v 3.3v power_on lvdm (hv) 0v lvdd (lv) 3.3v 0v power_ok 3.3v rc16mhz oscillator 0v 1.2v p0 idle 0v 1.2v internal reset generation module fsm v lvdhv3l v porh 0v
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 63/104 figure 12. brown-out typical sequence 3.10 nvusro register portions of the device configuration, such as high voltage supply, and watchdog enable/disable after reset are controlled via bit values in the non-volatile user options register (nvusro) register. for a detailed description of the nvusro register, please refer to the device reference manual. 3.10.1 nvusro[pad3v5v ] field description ta bl e 1 9 shows how nvusro[pad3v5v] controls the device configuration. the dc electrical characteristics are dependent on the pad3v5v bit value. vdd_hv_reg 0v 3.3v 0v 3.3v vdd_lv_regcor 0v 1.2v 3.3v power_on lvdm (hv) 0v lvdd (lv) 3.3v 0v power_ok 3.3v rc16mhz oscillator 0v 1.2v p0 idle 0v 1.2v internal reset generation module fsm v lvdhv3l 0v v lvdhv3h p1 ~1us table 19. pad3v5v field description (1) 1. see the device reference manual for mo re information on the nvusro register. value (2) 2. '1' is delivery value. it is part of s hadow flash, thus progr ammable by customer. description 0 high voltage supply is 5.0 v 1 high voltage supply is 3.3 v
electrical characteristics spc56xp54x, spc56xp60x 64/104 doc id 18340 rev 3 3.11 dc electrical characteristics 3.11.1 dc electrical characteristics (5 v) ta bl e 2 0 gives the dc electrical characteristics at 5 v (4.5 v < v dd_hv_iox < 5.5 v, nvusro[pad3v5v]=0) as described in figure 13 . figure 13. i/o input dc electrical characteristics definition v il v in v ih pdix = ?1? v dd v hys (gpdi register of siul) pdix = ?0? table 20. dc electrical characteristics (5.0 v, nvusro[pad3v5v]=0) symbol parameter conditions min max unit v il d minimum low level input voltage ? ?0.1 (1) ?v v il p maximum level input voltage ? ? 0.35 v dd_hv_iox v v ih p minimum high level input voltage ? 0.65 v dd_hv_iox ?v v ih d maximum high level input voltage ? ? v dd_hv_iox +0.1 (1) v v hys t schmitt trigger hysteresis ? 0.1 v dd_hv_iox ?v v ol_s p slow, low level output voltage i ol =3ma ? 0.1v dd_hv_iox v v oh_s p slow, high level output voltage i oh =?3ma 0.8v dd_hv_iox ?v v ol_m p medium, low level output voltage i ol =3ma ? 0.1v dd_hv_iox v v oh_m p medium, high level output voltage i oh =?3ma 0.8v dd_hv_iox ?v v ol_f p fast, low level output voltage i ol =3ma ? 0.1v dd_hv_iox v v oh_f p fast, high level output voltage i oh =?3ma 0.8v dd_hv_iox ?v v ol_sym p symmetric, low level output voltage i ol =3ma ? 0.1v dd_hv_iox v v oh_sym p symmetric, high level output voltage i oh =?3ma 0.8v dd_hv_iox ?v
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 65/104 i pu p equivalent pull-up current v in =v il ?130 ? a v in =v ih ??10 i pd p equivalent pull-down current v in =v il 10 ? a v in =v ih ?130 i il p input leakage current (all bidirectional ports) t a = ?40 to 125 c ?1 1 a i il p input leakage current (all adc input-only ports) t a = ?40 to 125 c ?0.5 0.5 a c in d input capacitance ? ? 10 pf i pu d reset , equivalent pull-up current v in =v il ?130 ? a v in =v ih ??10 i pd d reset , equivalent pull-down current v in =v il 10 ? a v in =v ih ?130 1. ?sr? parameter values must not exc eed the absolute maximum ratings shown in table 9 . table 20. dc electrical characteristics (5.0 v, nvusro[pad3v5v]=0) (continued) symbol parameter conditions min max unit
electrical characteristics spc56xp54x, spc56xp60x 66/104 doc id 18340 rev 3 table 21. supply current (5.0 v, nvusro[pad3v5v]=0) symbol parameter conditions value unit typ max i dd_lv_core t supply current run ? maximum mode (1) v dd_lv_core externally forced at 1.3 v adc freq = 32 mhz pll freq = 64 mhz 64 mhz 90 120 ma run - platform consumption, single core (2) vdd_lv_core externally forced to 1.3v 16 mhz 21 37 40 mhz 35 55 64 mhz 48 72 run - platform consumption, dual core (3) 16 mhz 24 41 40 mhz 42 64 64 mhz 58 85 p run ? maximum mode (4) v dd_lv_core externally forced at 1.3 v 64 mhz 85 113 halt mode (5) v dd_lv_core externally forced at 1.3 v ?5.515 stop mode (6) v dd_lv_core externally forced at 1.3 v ?4.513 i dd_flash t flash memory supply current during read v dd_hv_fl at 5.0 v ? ? 14 flash memory supply current during erase operation on 1 flash memory module v dd_hv_fl at 5.0 v ? ? 42 i dd_adc t adc supply current ? maximum mode v dd_hv_ad at 5.0 v adc freq = 16 mhz ?34 i dd_osc t osc supply current v dd_osc at 5.0v 8mhz 2.6 3.2 1. maximum mode configuration: code fetched from flash executed by dual core, siul, pit, adc_0, etimer_0/1, linflex_0/1, stm, intc_0/1, dspi_0/1/2/3/4, flexcan_0/ 1, flexray (static consumpt ion), crc_0/1, fccu, sram enabled. i/o supply current excluded. 2. ram, code and data flash powered, code fetched from flas h executed by single core, all peripherals gated; irc16mhz on, pll64mhz off(except for code running at 64mhz). code is performing continous dat a transfet from flash to ram. 3. ram, code and data flash powered, code fetched from flash executed by dual core, all pe ripherals gated; irc16mhz on, pll64mhz off(except fo r code running at 64mhz). code is performing continous dat a transfet from flash to ram. 4. maximum mode configuration: code fetched from ram ex ecuted by dual core, siul, pit, adc_0, etimer_0/1, linflex_0/1, stm, intc_0/1, dspi_0/1/2/3/4, flexcan_0/ 1, flexray (static consumpt ion), crc_0/1, fccu, sram enabled. i/o supply current excluded. 5. halt mode configuration, only for the ?p? classification: c ode flash memory in low power mode, data flash memory in power down mode, osc/pll are off, firc is on , core clock gated, all peripherals are disabled. 6. stop mode configuration, only for th e ?p? classification: code and data flash memories in power down mode, osc/pll are off, firc is on, core clock gated, all peripher als are disabled.
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 67/104 3.11.2 dc electrical characteristics (3.3 v) ta bl e 2 2 gives the dc electrical characteristics at 3.3 v (3.0 v < v dd_hv_iox < 3.6 v, nvusro[pad3v5v]=1) as described in figure 14 . figure 14. i/o input dc electrical characteristics definition v il v in v ih pdix = ?1? v dd v hys (gpdi register of siul) pdix = ?0? table 22. dc electrical characteristics (3.3 v, nvusro[pad3v5v]=1) (1) symbol parameter con ditions min max unit v il d minimum low level input voltage ? ?0.1 (2) ?v v il p maximum low level input voltage ? ? 0.35 v dd_hv_iox v v ih p minimum high level input voltage ? 0.65 v dd_hv_iox ?v v ih d maximum high level input voltage ? ? v dd_hv_iox +0.1 (2) v v hys t schmitt trigger hysteresis ? 0.1 v dd_hv_iox ?v v ol_s p slow, low level output voltage i ol =1.5ma ? 0.5 v v oh_s p slow, high level output voltage i oh =?1.5ma v dd_hv_iox ?0.8 ? v v ol_m p medium, low level output voltage i ol =2ma ? 0.5 v v oh_m p medium, high level output voltage i oh =?2ma v dd_hv_iox ?0.8 ? v v ol_f p fast, high level output voltage i ol =1.5ma ? 0.5 v v oh_f p fast, high level output voltage i oh =?1.5ma v dd_hv_iox ?0.8 ? v v ol_sym p symmetric, high level output voltage i ol =1.5ma ? 0.5 v v oh_sym p symmetric, high level output voltage i oh =?1.5ma v dd_hv_iox ?0.8 ? v i pu p equivalent pull-up current v in =v il ?130 ? a v in =v ih ? ?10
electrical characteristics spc56xp54x, spc56xp60x 68/104 doc id 18340 rev 3 i pd p equivalent pull-down current v in =v il 10 ? a v in =v ih ? 130 i il p input leakage current (all bidirectional ports) t a = ?40 to 125 c ? 1 a i il p input leakage current (all adc input-only ports) t a = ?40 to 125 c ? 0.5 a c in d input capacitance ? ? 10 pf i pu d reset , equivalent pull-up current v in =v il ?130 ? a v in =v ih ? ?10 i pd d reset , equivalent pull-down current v in =v il 10 ? a v in =v ih ? 130 1. these specifications are des ign targets and subject to ch ange per device characterization. 2. ?sr? parameter values must not exc eed the absolute maximum ratings shown in table 9 . table 22. dc electrical characteristics (3.3 v, nvusro[pad3v5v]=1) (1) (continued) symbol parameter con ditions min max unit
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 69/104 table 23. supply current (3.3 v, nvusro[pad3v5v]=1) symbol parameter conditions value unit typ max i dd_lv_core t supply current run ? maximum mode (1) v dd_lv_core externally forced at 1.3 v adc freq = 32 mhz pll freq = 64 mhz 64 mhz 90 120 ma run - platform consumption, single core (2) vdd_lv_core externally forced to 1.3v 16 mhz 21 37 40 mhz 35 55 64 mhz 48 72 run - platform consumption, dual core (3) 16 mhz 24 41 40 mhz 42 64 64 mhz 58 85 p run ? maximum mode (4) v dd_lv_core externally forced at 1.3 v 64 mhz 85 113 halt mode (5) v dd_lv_core externally forced at 1.3 v ?5.515 stop mode (6) v dd_lv_core externally forced at 1.3 v ?4.513 i dd_flash d flash memory supply current during read v dd_hv_fl at 3.3 v ? ? 14 flash memory supply current during erase operation on 1 flash memory module v dd_hv_fl at 3.3 v ? ? 42 i dd_adc t adc supply current ? maximum mode v dd_hv_ad at 3.3 v adc freq = 16 mhz ?34 i dd_osc t osc supply current v dd_osc at 3.3 v 8 mhz 2.4 3 1. maximum mode configuration: code fetched from flash executed by dual core, siul, pit, adc_0, etimer_0/1, linflex_0/1, stm, intc_0/1, dspi_0/1/2/3/4, flexcan_0/ 1, flexray (static consumpt ion), crc_0/1, fccu, sram enabled. i/o supply current excluded. 2. ram, code and data flash powered, code fetched from flas h executed by single core, all peripherals gated; irc16mhz on, pll64mhz off(except for code running at 64mhz). code is performing continous dat a transfet from flash to ram. 3. ram, code and data flash powered, code fetched from flash executed by dual core, all pe ripherals gated; irc16mhz on, pll64mhz off(except fo r code running at 64mhz). code is performing continous dat a transfet from flash to ram. 4. maximum mode configuration: code fetched from ram ex ecuted by dual core, siul, pit, adc_0, etimer_0/1, linflex_0/1, stm, intc_0/1, dspi_0/1/2/3/4, flexcan_0/ 1, flexray (static consumpt ion), crc_0/1, fccu, sram enabled. i/o supply current excluded. 5. halt mode configuration, only for the ?p? classification: c ode flash memory in low power mode, data flash memory in power down mode, osc/pll are off, firc is on , core clock gated, all peripherals are disabled. 6. stop mode configuration, only for th e ?p? classification: code and data flash memories in power down mode, osc/pll are off, firc is on, core clock gated, all peripher als are disabled.
electrical characteristics spc56xp54x, spc56xp60x 70/104 doc id 18340 rev 3 table 24. peripherals supply current (5 v and 3.3 v) (1) symbol parameter conditions value unit typ max i dd_bv(can) t can (flexcan) supply current on vdd_bv 500 kbyte/s total (static + dynamic) consumption: ? flexcan in loop-back mode ? xtal@ 8 mhz used as can engine clock source ? message sending period is 580 s 21.6 * f periph 28.1* f periph a i dd_bv(sci) t sci (linflex) supply current on vdd_bv total (static + dynamic) consumption: ?lin mode ? baudrate: 115.2 kbyte/s 10.8 * f periph 14.1 * f periph i dd_bv(spi) t spi (dspi) supply current on vdd_bv ballast dynamic consumption (continuous communication): ? baudrate: 2 mbit/s ? transmission every 8 s ? frame: 16 bits 4.8 * f periph 6.3 * f periph i dd_bv(adc) t adc supply current on vdd_bv vdd = 5.5 v ballast dynamic consumption (continuous conversion) 120 * f periph 156 * f periph i dd_hv_adc(adc) t adc supply current on vdd_hv_adc vdd = 5.5 v analog dynamic consumption (continuous conversion) 0.005 * f periph + 2.8 0.007 * f periph + 3.4 ma i dd_bv(etimer) t etimer supply current on vdd_bv pwm signals generation on all 1 channel @10khz dynamic consumption does not change varying the frequency 1.8 2.4 ma i dd_bv(flexray) t flexray supply current on vdd_bv static consumption 4.2 * f periph 5.5 * f periph a 1. operating conditions: f periph = 8 mhz to 64 mhz
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 71/104 3.11.3 i/o pad cu rrent specification the i/o pads are distributed across the i/o supply segment. each i/o supply segment is associated to a v dd /v ss supply pair as described in ta bl e 2 5 . table 25. i/o supply segment package supply segment 12345 6 7 lqfp144 pin8 ? pin20 pin23 ? pin38 pin39 ? pin55 pin58 ? pin68 pin73 ? pin89 pin92 ? pin125 pin128 ? pin5 lqfp100 pin15 ? pin26 pin27 ? pin38 pin41 ? pin46 pin51 ? pin61 pin64 ? pin86 pin89 ? pin10 ? table 26. i/o consumption symbol c parameter conditions (1) value unit min typ max i swtslw (2) cc d dynamic i/o current for slow configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??20 ma v dd = 3.3 v 10%, pad3v5v = 1 ??16 i swtmed (2) cc d dynamic i/o current for medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??29 ma v dd = 3.3 v 10%, pad3v5v = 1 ??17 i swtfst (2) cc d dynamic i/o current for fast configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ? ? 110 ma v dd = 3.3 v 10%, pad3v5v = 1 ??50 i rmsslw cc d root medium square i/o current for slow configuration c l = 25 pf, 2 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??2.3 ma c l = 25 pf, 4 mhz ? ? 3.2 c l = 100 pf, 2 mhz ? ? 6.6 c l = 25 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??1.6 c l = 25 pf, 4 mhz ? ? 2.3 c l = 100 pf, 2 mhz ? ? 4.7 i rmsmed cc d root medium square i/o current for medium configuration c l = 25 pf, 13 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??6.6 ma c l = 25 pf, 40 mhz ? ? 13.4 c l = 100 pf, 13 mhz ? ? 18.3 c l = 25 pf, 13 mhz v dd = 3.3 v 10%, pad3v5v = 1 ?? 5 c l = 25 pf, 40 mhz ? ? 8.5 c l = 100 pf, 13 mhz ? ? 11
electrical characteristics spc56xp54x, spc56xp60x 72/104 doc id 18340 rev 3 3.12 main oscillator elec trical characteristics the spc56xp54/60 provides an oscillator/reso nator driver. i rmsfst cc d root medium square i/o current for fast configuration c l = 25 pf, 40 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??22 ma c l = 25 pf, 64 mhz ? ? 33 c l = 100 pf, 40 mhz ? ? 56 c l = 25 pf, 40 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??14 c l = 25 pf, 64 mhz ? ? 20 c l = 100 pf, 40 mhz ? ? 35 i avgseg sr d sum of all the static i/o current within a supply segment v dd = 5.0 v 10%, pad3v5v = 0 ? ? 70 ma v dd = 3.3 v 10%, pad3v5v = 1 ? ? 65 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 125 c, unless otherwise specified 2. stated maximum values represent peak consumption that lasts only a few ns during i/o transition. table 26. i/o consumption (continued) symbol c parameter conditions (1) value unit min typ max table 27. main oscillator electrical char acteristics (5.0 v, nvusro[pad3v5v]=0) symbol parameter min max unit f osc sr oscillator frequency 4 40 mhz g m p transconductance 6.5 25 ma/v v osc t oscillation amplitude on extal pin 1 ? v t oscsu t start-up time (1),(2) 1. the start-up time is dependent upon crystal characte ristics, board leakage, et c., high esr and excessive capacitive loads can c ause long start-up time. 2. value captured when amplitude reaches 90% of extal 8?ms table 28. main oscillator electrical char acteristics (3.3 v, nvusro[pad3v5v]=1) symbol parameter min max unit f osc sr oscillator frequency 4 40 mhz g m p transconductance 4 20 ma/v v osc t oscillation amplitude on extal pin 1 ? v t oscsu t start-up time (1),(2) 1. the start-up time is dependent upon crystal characte ristics, board leakage, et c., high esr and excessive capacitive loads can c ause long start-up time. 2. value captured when amplitude reaches 90% of extal 8?ms
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 73/104 3.13 fmpll electrical characteristics table 29. input clock characteristics symbol parameter min typ max unit f osc sr oscillator frequency 4 ? 40 mhz f clk sr frequency in bypass ? ? 64 mhz t rclk sr rise/fall time in bypass ? ? 1 ns t dc sr duty cycle 47.5 50 52.5 % table 30. pllmrfm electrical specifications (v ddpll = 1.08 v to 1.32 v, v ss = v sspll = 0 v, t a = t l to t h ) symbol parameter conditions value unit min max f ref_crystal f ref_ext d pll reference frequency range (1) crystal reference 4 40 mhz f pll_in d phase detector input frequency range (after pre-divider) ?416mhz f fmpllout d clock frequency range in normal mode ? 4 120 mhz f free p free running frequency measured using clock division ? typically /16 20 150 mhz f sys d on-chip pll frequency ? 16 64 mhz t cyc d system clock period ? ? 1 / f sys ns f lorl f lorh d loss of reference frequency window (2) lower limit 1.6 3.7 mhz upper limit 24 56 f scm d self-clocked mode frequency (3),(4) ?20150mhz c jitter t clkout period jitter (5),(6),(7),(8) short-term jitter (9) f sys maximum ?4 4 % f clkout long-term jitter (avg. over 2 ms interval) f pllin = 16 mhz (resonator) , f pllclk at 64 mhz, 4000 cycles ?10 ns t lpll dpll lock time (10), (11) ??200s t dc d duty cycle of reference ?4060% f lck d frequency lock range ? ?6 6 % f sys f ul d frequency un-lock range ? ?18 18 % f sys f cs f ds d modulation depth center spread 0.25 4.0 (12) %f sys down spread ?0.5 ?8.0 f mod d modulation frequency (13) ??70khz 1. considering operation with pll not bypassed.
electrical characteristics spc56xp54x, spc56xp60x 74/104 doc id 18340 rev 3 3.14 16 mhz rc oscillator el ectrical characteristics 3.15 analog-to-digital converter (adc) electrical characteristics the device provides a 10-bit successive approximation register (sar) analog-to-digital converter. 2. ?loss of reference frequency? window is the reference frequency range outside of which the pll is in self clocked mode. 3. self clocked mode frequency is the frequency that the pll op erates at when the reference frequency falls outside the f lor window. 4. f vco self clock range is 20?150 mhz. f scm represents f sys after pll output divider (erfd) of 2 through 16 in enhanced mode. 5. this value is determined by the crystal manufacturer and board design. 6. jitter is the average deviation from t he programmed frequency measured over t he specified interval at maximum f sys . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddpll and v sspll and variation in crystal osci llator frequency increase the c jitter percentage for a given interval. 7. proper pc board layout procedures must be followed to achieve specifications. 8. values are obtained with frequency modulation disabled. if frequency modulation is enabled, jitter is the sum of c jitter and either f cs or f ds (depending on whether center spread or down spread modulation is enabled). 9. short term jitter is measured on the cl ock rising edge at cy cle n and cycle n+4. 10. this value is determined by the crystal manufacturer and board design. for 4 mhz to 20 mhz crystals specified for this pll, load capacitors should not exceed these limits. 11. this specification applies to the period required for the p ll to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). 12. this value is true when operating at frequencies above 60 mhz, otherwise f cs is 2% (above 64 mhz). 13. modulation depth will be attenuated from depth setti ng when operating at modulation frequencies above 50 khz. table 31. 16 mhz rc oscillator electrical characteristics symbol parameter conditions min typ max unit f rc p rc oscillator frequency t a = 25 c ? 16 ? mhz ? rcmvar p fast internal rc oscillator variation over temperature and supply with respect to f rc at t a = 25 c in high-frequency configuration ??6?6% ? rcmtrim t post trim accuracy: the variation of the ptf (1) from the 16 mhz t a = 25 c ?1 ? 1 % ? rcmstep t fast internal rc oscillator trimming step t a = 25 c ? 1.6 ? % 1. ptf = post trimming frequency: the frequency of the output clock after trimming at typical supply voltage and temperature
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 75/104 figure 15. adc characteristics and error definitions 3.15.1 input impedance and adc accuracy to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacitor with good high-frequency characteristics at the input pin of the device can be effective: the capa citor should be as large as possible, ideally infinite. this capacitor contributes to attenuate the noise present on the input pin; further, it sources charge during the sampling phase, when the analog signal source is a high- impedance source. a real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple rc filter). the rc filtering may be limited according to the source impedance value of the transducer or circuit supplying the analog signal to be measured. (2) (1) (3) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 1023 1022 1021 1020 1019 1018 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 1 lsb ideal = v dd_adc / 1024
electrical characteristics spc56xp54x, spc56xp60x 76/104 doc id 18340 rev 3 the filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the adc itself. in fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: being c s and c p2 substantially two switched capacitances, with a frequency equal to the adc conversion rate, it can be seen as a resistive path to ground. for instance, assuming a conversion rate of 1 mhz, with c s + c p2 equal to 3 pf, a resistance of 330 k ? is obtained (r eq = 1 / (fc (c s + c p2 )), where fc represents the conversion rate at the considered channel). to minimize the error induced by the voltage partitioning between this resistance (sampled voltage on c s + c p2 ) and the sum of r s + r f , the external circuit must be designed to respect the equation 4 : equation 4 equation 4 generates a constraint for external network design, in particular on resistive path. internal switch resistances (r sw and r ad ) can be neglected with respect to external resistances. figure 16. input equivalent circuit (precise channels) v a r s r f + r eq --------------------- ? 1 2 -- - lsb ? r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw1 channel selection switch impedance r ad sampling switch impedance c p pin capacitance (two contributions, c p1 and c p2 ) c s sampling capacitance c p1 r ad channel selection v a
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 77/104 figure 17. input equivalent circuit (extended channels) a second aspect involving the capacitance network shall be considered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the equivalent circuit reported in figure 16 ): a charge sharing phenomenon is installed when the sampling phase is started (a/d switch close). figure 18. transient behavior during sampling phase r f c f r s r l r sw1 c p3 c s v dd sampling source filter current limiter external circuit internal circuit scheme c p1 r ad channel selection v a c p2 extended r sw2 switch r s : source impedance r f : filter resistance c f : filter capacitance r l : current limiter resistance r sw1 : channel selection switch impedance (two contributions, r sw1 and r sw2 ) r ad : sampling switch impedance c p : pin capacitance (two contributions, c p1 , c p2 and c p3 ) c s : sampling capacitance v a v a1 v a2 t t s v cs voltage transient on c s ? v < ? 0.5 lsb ? 1 2 ? 1 < (r sw + r ad ) c s << t s ? 2 = r l (c s + c p1 + c p2 )
electrical characteristics spc56xp54x, spc56xp60x 78/104 doc id 18340 rev 3 in particular two different transient periods can be distinguished: a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely discharged): considering a worst case (since the time cons tant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is equation 5 equation 5 can again be simplified considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: equation 6 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 7 : equation 7 a second charge transfer involves also c f (that is typically bigger than the on-chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: equation 8 in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraint on r l sizing is obtained: equation 9 of course, r l shall be sized also according to the current limitation constraints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer transient) will be much higher than v a1 . equation 10 must be respected (charge balance assuming now c s already charged at v a1 ): equation 10 the two transients above are not influenced by the voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to compensate the voltage drop on ? 1 r sw r ad + ?? c p c s ? c p c s + --------------------- - ? = ? 1 r sw r ad + ?? c s t s ? ? ? ++ ?? ? v a c p1 c p2 + ?? ? = ? 2 r l c s c p1 c p2 ++ ?? ? ? ? 2 ? 8.5 r l c s c p1 c p2 ++ ?? ? ? = t s ? +++ ?? ? v a c f ? v a1 c p1 c p2 + c s + ?? ? + =
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 79/104 c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is typically designed to act as anti-aliasing. figure 19. spectral representation of input signal calling f 0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new c onstraints on the external circuit, to reduce the accuracy error due to the voltage drop on c s ; from the two charge balance equations above, it is simple to derive equation 11 between the ideal and real sampled voltage on c s : equation 11 from this formula, in the worst case (when v a is maximum, that is for instance 5 v), assuming to accept a maximum error of half a count, a constraint is evident on c f value: equation 12 f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 ?? f c (nyquist) f f ? f 0 (anti-aliasing filtering condition) t c ?? 2 r f c f (conversion rate vs. filter pole) noise v a v a2 ---------- c p1 c p2 + c f + c p1 c p2 + c f c s ++ ------------------------------------------------------- - = c f 2048 c s ? ?
electrical characteristics spc56xp54x, spc56xp60x 80/104 doc id 18340 rev 3 3.15.2 adc conversion characteristics table 32. adc conversion characteristics symbol parameter conditions (1) value unit min typ max v inan sr analog input voltage (2) ? v ss_hv_ad ? ?? 0.3 ? v ss_hv_ad + 0.3 v f ck sr adc clock frequency (depends on adc configuration) (the duty cycle depends on ad_clk (3) frequency) ?3 (4) ?60mhz f s sr sampling frequency ? ? ? 1.53 mhz t adc_s d sample time (5) f adc = 20 mhz, inpsamp = 3 125 ? ? ns f adc = 9 mhz, inpsamp = 255 ??28.2s t adc_c pconversion time (6) f adc = 20 mhz (7) , inpcmp = 1 0.650 ? ? s c s (8) d adc input sampling capacitance ???2.5pf c p1 (8) d adc input pin capacitance 1 ???3pf c p2 (8) d adc input pin capacitance 2 ???1pf c p3 (8) d adc input pin capacitance 3 ???1pf r sw1 (8) d internal resistance of analog source v dd_hv_ad = 5 v 10% ? ? 0.6 k ? v dd_hv_ad = 3.3 v 10% ? ? 3 k ? r sw2 (8) d internal resistance of analog source v dd_hv_ad = 5 v 10% ? ? 2.15 k ? v dd_hv_ad = 3.3 v 10% ? ? 3.6 k ? r ad (8) d internal resistance of analog source ???2k ? i inj t input current injection current injection on one adc input, different from the converted one. remains within tue spec. ?5 ? 5 ma inl p integral non linearity no overload ? 1.5 ? lsb dnl p differential non linearity no overload ?1.0 ? 1.0 lsb ofs t offset error ? ? 1 ? lsb gne t gain error ? ? 1 ? lsb tue p total unadjusted error without current injection 16 precision channels ?2.5 ? 2.5 lsb
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 81/104 3.16 flash memory elect rical characteristics tue t total unadjusted error with current injection 16 precision channels ?3 ? 3 lsb tue t total unadjusted error with current injection 10 standard channels ?4 ? 4 lsb 1. v dd = 3.3 v to 3.6 v / 4.5 v to 5.5 v, t a = ?40 c to t a max , unless otherwise specified and analog input voltage from v ss_hv_ad to v dd_hv_ad . 2. v inan may exceed v ss_adc and v dd_adc limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3ff. 3. ad_clk clock is always half of the adc module input clock defined via t he auxiliary clock divider for the adc. 4. when configured to allow 60 mhz adc, the minimum adc clock speed is 9 mhz, below which precision is lost. 5. during the sample time the input capacitance cs can be charged/discharged by the exte rnal source. the internal resistance of the analog source must allow the capacitance to reach its fi nal voltage level within t adc_s . after the end of the sample time t adc_s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t adc_s depend on programming. 6. this parameter includes the sample time t adc_s . 7. 20 mhz adc clock. specific pre scaler is programmed on mc_pll_clk to provide 20 mhz clock to the adc. 8. see figure 16 . table 32. adc conversion characteristics (continued) symbol parameter conditions (1) value unit min typ max table 33. program and erase specifications symbol parameter conditions value unit min typ (1) initial max (2) max (3) t wprogram p word program (32 bits) time (4) data flash ? 30 70 500 s t dwprogram p double word (64 bits) program time (4) code flash ? 18 50 500 s t bkprg p bank program (64 kb) (4), (5) data flash ? 0.49 1.2 4.1 s p bank program (1056 kb) (4), (5) code flash ? 2.6 6.6 66 s t mdprg p module program (512 kb) (4) code flash ? 1.3 1.65 33 s t 16kpperase p 16 kb block pre-program and erase time code flash ? 200 500 5000 ms data flash 700 800 t 32kpperase p 32 kb block pre-program and erase time code flash ? 300 600 5000 ms t 64kpperase p 64 kb block pre-program and erase time code flash ? 400 900 5000 ms t 128kpperase p 128 kb block pre-program and erase time code flash ? 600 1300 5000 ms t esrt p erase suspend request rate (6) code flash 20 ?? ?ms data flash 10 1. typical program and erase ti mes assume nominal supply values and operati on at 25 c. all times are subject to change pending device characterization. 2. initial factory condition: < 100 program/e rase cycles, 25 c, typical supply voltage.
electrical characteristics spc56xp54x, spc56xp60x 82/104 doc id 18340 rev 3 3. the maximum program and erase times occu r after the specified number of program /erase cycles. these maximum values are characterized but not guaranteed. 4. actual hardware programming times. this does not include software overhead. 5. typical bank programming ti me assumes that all cells are programmed in a sing le pulse. in reality so me cells will require more than one pulse, adding a small overhead to tota l bank programming time (see initial max column). 6. time between erase suspend resume and next erase suspend. table 34. flash memory module life symbol parameter conditions value unit min typ p/e c number of program/erase cycles per block for 16 kb blocks over the operating temperature range (t j ) ? 100000 100000 cycles p/e c number of program/erase cycles per block for 32 kb blocks over the operating temperature range (t j ) ? 10000 100000 cycles p/e c number of program/erase cycles per block for 64 kb blocks over the operating temperature range (t j ) ? 10000 100000 cycles p/e c number of program/erase cycles per block for 128 kb blocks over the operating temperature range (t j ) ? 1000 100000 cycles retention c minimum data retention at 85 c average ambient temperature (1) blocks with 0 ? 1000 p/e cycles 20 ? years blocks with 10000 p/e cycles 10 ? years blocks with 100000 p/e cycles 5?years 1. ambient temperature averaged over dur ation of application, not to exceed recommended product operating temperature range. table 35. flash read access timing symbol c parameter conditions (1) 1. vdd = 3.3 v 10% / 5.0 v 10%, ta = ?40 to 125 c, unless otherwise specified max unit fmax c maximum working frequency for code flash at given number of ws in worst conditions 2 wait states 66 mhz 0 wait states 22 fmax c maximum working frequency for data flash at given number of ws in worst conditions 8 wait states 66 mhz
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 83/104 3.17 ac specifications 3.17.1 pad ac specifications 3.18 ac timing characteristics 3.18.1 reset pin characteristics the spc56xp54/60 implements a de dicated bidirectional reset pin. table 36. output pin transition times symbol c parameter conditions (1) value unit min typ max t tr cc d output transition time output pin (2) slow configuration c l = 25 pf v dd = 5.0 v 10%, pa d 3 v 5 v = 0 ??50 ns tc l = 50 pf ? ? 100 dc l = 100 pf ? ? 125 dc l = 25 pf v dd = 3.3 v 10%, pa d 3 v 5 v = 1 ??40 tc l = 50 pf ? ? 50 dc l = 100 pf ? ? 75 t tr cc d output transition time output pin (2) medium configuration c l = 25 pf v dd = 5.0 v 10%, pa d 3 v 5 v = 0 siul.pcrx.src = 1 ??10 ns tc l = 50 pf ? ? 20 dc l = 100 pf ? ? 40 dc l = 25 pf v dd = 3.3 v 10%, pa d 3 v 5 v = 1 siul.pcrx.src = 1 ??12 tc l = 50 pf ? ? 25 dc l = 100 pf ? ? 40 t tr cc d output transition time output pin (2) fast configuration c l = 25 pf v dd = 5.0 v 10%, pa d 3 v 5 v = 0 siul.pcrx.src = 1 ?? 4 ns c l = 50 pf ? ? 6 c l = 100 pf ? ? 12 c l = 25 pf v dd = 3.3 v 10%, pa d 3 v 5 v = 1 siul.pcrx.src = 1 ?? 4 c l = 50 pf ? ? 7 c l = 100 pf ? ? 12 t sim (3) cc t symmetric, same drive strength between n and p transistor v dd = 5.0 v 10%, pad3v5v = 0 ? ? 4 ns v dd = 3.3 v 10%, pad3v5v = 1 ? ? 5 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 c to t a max , unless otherwise specified 2. c l includes device and package capacitances (c pkg < 5 pf). 3. transition timing of bot h positive and negative slopes will differ maximum 50%
electrical characteristics spc56xp54x, spc56xp60x 84/104 doc id 18340 rev 3 figure 20. start-up reset requirements (f) figure 21. noise filtering on reset signal f. the output drive provided is open dr ain and hence must be terminated by an external resistor of value 1 k ?? v il v dd device reset forced by v reset v ddmin v reset v ih device start-up phase t por v r e s e t v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 85/104 table 37. reset electrical characteristics symbol c parameter conditions (1) value unit min typ max v ih sr p input high level cmos (schmitt trigger) ? 0.65v dd ?v dd +0.4 v v il sr p input low level cmos (schmitt trigger) ? ? 0.4 ? 0.35v dd v v hys cc c input hysteresis cmos (schmitt trigger) ?0.1v dd ?? v v ol cc p output low level push pull, i ol = 2ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v push pull, i ol = 1ma, v dd = 5.0 v 10%, pad3v5v = 1 (2) ? ? 0.1v dd push pull, i ol = 1ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 t tr cc d output transition time output pin (3) medium configuration c l = 25pf, v dd = 5.0 v 10%, pad3v5v = 0 ??10 ns c l = 50pf, v dd = 5.0 v 10%, pad3v5v = 0 ??20 c l = 100pf, v dd = 5.0 v 10%, pad3v5v = 0 ??40 c l = 25pf, v dd = 3.3 v 10%, pad3v5v = 1 ??12 c l = 50pf, v dd = 3.3 v 10%, pad3v5v = 1 ??25 c l = 100pf, v dd = 3.3 v 10%, pad3v5v = 1 ??40 w frst sr p reset input filtered pulse ? ? ? 40 ns w nfrst sr p reset input not filtered pulse ?500??ns t por cc d maximum delay before internal reset is released after all vdd_hv reach nominal supply monotonic vdd_hv supply ramp ? ? 1 ms |i wpu |ccp weak pull-up current absolute value v dd = 3.3 v 10%, pad3v5v = 1 10 ? 150 a v dd = 5.0 v 10%, pad3v5v = 0 10 ? 150 v dd = 5.0 v 10%, pad3v5v = 1 (4) 10 ? 250 1. v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 c to t a max , unless otherwise specified 2. this is a transient configuration duri ng power-up, up to the end of reset phase2 (refer to rgm module section of device reference manual). 3. c l includes device and package capacitance (c pkg <5pf). 4. the configuration pad3v5 = 1 when v dd = 5 v is only transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are conf igured in input or in high impedance state.
electrical characteristics spc56xp54x, spc56xp60x 86/104 doc id 18340 rev 3 3.18.2 ieee 1149.1 interface timing figure 22. jtag test clock input timing table 38. jtag pin ac electrical characteristics no. symbol c parameter c onditions min max unit 1t jcyc cc d tck cycle time ? 100 ? ns 2t jdc cc d tck clock pulse width (measured at v dd_hv_iox /2) ? 40 60 ns 3t tckrise cc d tck rise and fall times (40% ? 70%) ? ? 3 ns 4t tmss, t tdis cc d tms, tdi data setup time ? 5 ? ns 5t tmsh, t tdih cc d tms, tdi data hold time ? 25 ? ns 6t tdov cc d tck low to tdo data valid ? ? 40 ns 7t tdoi cc d tck low to tdo data invalid ? 0 ? ns 8t tdohz cc d tck low to tdo high impedance ? 40 ? ns 9t bsdv cc d tck falling edge to output valid ? ? 50 ns 10 t bsdvz cc d tck falling edge to output valid out of high impedance ? ? 50 ns 11 t bsdhz cc d tck falling edge to output high impedance ? ? 50 ns 12 t bsdst cc d boundary scan input valid to tck rising edge ? 50 ? ns 13 t bsdht cc d tck rising edge to boundary scan input invalid ? 50 ? ns tck 1 2 2 3 3
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 87/104 figure 23. jtag test access port timing tck 4 5 6 7 8 tms, tdi tdo
electrical characteristics spc56xp54x, spc56xp60x 88/104 doc id 18340 rev 3 figure 24. jtag boundary scan timing 3.18.3 nexus timing tck output signals input signals output signals 10 11 12 13 9 table 39. nexus debug port timing (1) no. symbol c parameter value unit min typ max 1t mcyc cc d mcko cycle time 32 ? ? ns 2t mdov cc d mcko edge to mdo data valid ? 0.1 t mcyc ?0.25t mcyc ns 3t mseov cc d mcko edge to mseo data valid ? 0.1 t mcyc ?0.25t mcyc ns 4t evtov cc d mcko edge to evto data valid ? 0.1 t mcyc ?0.25t mcyc ns 5t tcyc cc d tck cycle time 64 (2) ?? ns
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 89/104 figure 25. nexus output timing figure 26. nexus event trigger and test clock timings 6 t ntdis cc d tdi data setup time 6 ? ? ns t ntmss cc d tms data setup time 6 ? ? ns 7 t ntdih cc d tdi data hold time 10 ? ? ns t ntmsh cc d tms data hold time 10 ? ? ns 8t tdov cc d tck low to tdo data valid ? ? 35 ns 9t tdoi cc d tck low to tdo data invalid 6 ? ? ns 1. all values need to be confir med during device validation. 2. lower frequency is required to be fully compliant to standard. table 39. nexus debug port timing (1) (continued) no. symbol c parameter value unit min typ max 1 3 4 mcko mdo mseo evto output data valid 2 tck 5 evti evto
electrical characteristics spc56xp54x, spc56xp60x 90/104 doc id 18340 rev 3 figure 27. nexus tdi, tms, tdo timing 3.18.4 external interr upt timing (irq pin) tdo 6 7 tms, tdi 8 tck 9 table 40. external interrupt timing (1) no. symbol c parameter conditions min max unit 1t ipwl cc d irq pulse width low ? 4 ? t cyc 2t ipwh cc d irq pulse width high ? 4 ? t cyc 3t icyc cc d irq edge to edge time (2) ?4 + n (3) ?t cyc 1. irq timing specified at f sys = 64 mhz and v dd_hv_iox = 3.0 v to 5.5 v, t a = t l to t h , and cl = 200pf with src = 0b00. 2. applies when irq pins are configured for rising edge or falling edge events, but not both. 3. n= isr time to clear the flag.
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 91/104 figure 28. external interrupt timing 3.18.5 dspi timing irq 2 3 1 table 41. dspi timing (1) no. symbol c parameter conditions min max unit 1t sck cc d dspi cycle time master (mtfe = 0) 60 ? ns slave (mtfe = 0) 60 ? 2t csc cc d pcs to sck delay ? 16 ? ns 3t asc cc d after sck delay ? 26 ? ns 4t sdc cc d sck duty cycle ? 0.4 t sck 0.6 t sck ns 5t a cc d slave access time ss active to sout valid ? 30 ns 6t dis cc d slave sout disable time ss inactive to sout high-z or invalid ? 16 ns 7t pcsc cc d pcsx to pcss time ? 13 ? ns 8t pasc ccdpcss to pcsx time ? 13 ? ns 9t sui cc d data setup time for inputs master (mtfe = 0) 35 ? ns slave 4? master (mtfe = 1, cpha = 0) 35 ? master (mtfe = 1, cpha = 1) 35 ? 10 t hi cc d data hold time for inputs master (mtfe = 0) ?5 ? ns slave 4 ? master (mtfe = 1, cpha = 0) 11 ? master (mtfe = 1, cpha = 1) ?5 ? 11 t suo cc d data valid (after sck edge) master (mtfe = 0) ? 12 ns slave ? 36 master (mtfe = 1, cpha = 0) ? 12 master (mtfe = 1, cpha = 1) ? 12
electrical characteristics spc56xp54x, spc56xp60x 92/104 doc id 18340 rev 3 figure 29. dspi classic spi timing ? master, cpha = 0 12 t ho cc d data hold time for outputs master (mtfe = 0) ?2 ? ns slave 6 ? master (mtfe = 1, cpha = 0) 6 ? master (mtfe = 1, cpha = 1) ?2 ? 1. all timing are provided with 50pf capacitance on output, 1ns transition time on input signal table 41. dspi timing (1) (continued) no. symbol c parameter conditions min max unit data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol=0) (cpol=1) 3 2
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 93/104 figure 30. dspi classic spi timing ? master, cpha = 1 figure 31. dspi classic spi timing ? slave, cpha = 0 data last data first data sin sout 12 11 10 last data data first data sck output sck output csx 9 (cpol=0) (cpol=1) last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol=0) (cpol=1)
electrical characteristics spc56xp54x, spc56xp60x 94/104 doc id 18340 rev 3 figure 32. dspi classic spi timing ? slave, cpha = 1 figure 33. dspi modified transfer format timing ? master, cpha = 0 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol=0) (cpol=1)
spc56xp54x, spc56xp60x electrical characteristics doc id 18340 rev 3 95/104 figure 34. dspi modified transfer format timing ? master, cpha = 1 figure 35. dspi modified transfer format timing ? slave, cpha = 0 pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol=0) (cpol=1) last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol=0) (cpol=1) 12
electrical characteristics spc56xp54x, spc56xp60x 96/104 doc id 18340 rev 3 figure 36. dspi modified transfer format timing ? slave, cpha = 1 figure 37. dspi pcs strobe (pcss ) timing 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) pcsx 7 8 pcss
spc56xp54x, spc56xp60x package characteristics doc id 18340 rev 3 97/104 4 package characteristics 4.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 4.2 package mechanical data 4.2.1 lqfp144 mechani cal outline drawing figure 38. lqfp144 package mechanical drawing d1 d3 d e1 e3 e e pin 1 identification 73 72 37 36 109 144 108 1 aa2a1 b c a1 l l1 k seating plane c ccc c 0.25 mm gage plane me_1a
package characteristics spc56xp54x, spc56xp60x 98/104 doc id 18340 rev 3 table 42. lqfp144 mechanical data symbol mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a ? ? 1.600 ? ? 0.0630 a1 0.050 ? 0.150 0.0020 ? 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 ? 0.200 0.0035 ? 0.0079 d 21.800 22.000 22.200 0.8583 0.8661 0.8740 d1 19.800 20.000 20.200 0.7795 0.7874 0.7953 d3 ? 17.500 ? ? 0.6890 ? e 21.800 22.000 22.200 0.8583 0.8661 0.8740 e1 19.800 20.000 20.200 0.7795 0.7874 0.7953 e3 ? 17.500 ? ? 0.6890 ? e ? 0.500 ? ? 0.0197 ? l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 ? 1.000 ? ? 0.0394 ? k 0.0 3.5 7.0 3.5 0.0 7.0 ccc (2) 2. tolerance 0.080 0.0031
spc56xp54x, spc56xp60x package characteristics doc id 18340 rev 3 99/104 4.2.2 lqfp100 mechani cal outline drawing figure 39. lqfp100 package mechanical drawing d d1 d3 75 51 50 76 100 26 125 e3 e1 e e b pin 1 identification seating plane gage plane c a a2 a1 c ccc 0.25 mm 0.10 inch l l1 k c 1l_me table 43. lqfp100 mechanical data symbol mm inches (1) min typ max min typ max a ? ? 1.600 ? ? 0.0630 a1 0.050 ? 0.150 0.0020 ? 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571
package characteristics spc56xp54x, spc56xp60x 100/104 doc id 18340 rev 3 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 ? 0.200 0.0035 ? 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 ? 12.000 ? ? 0.4724 ? e 15.800 16.000 16.200 0.6220 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 ? 12.000 ? ? 0.4724 ? e ? 0.500 ? ? 0.0197 ? l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 ? 1.000 ? ? 0.0394 ? k 0.0 3.5 7.0 0.0 3.5 7.0 ccc (2) 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. 2. tolerance table 43. lqfp100 mechanical data (continued) symbol mm inches (1) min typ max min typ max
spc56xp54x, spc56xp60x ordering information doc id 18340 rev 3 101/104 5 ordering information figure 40. ordering information scheme (g) g. not all configurations are avai lable on the market. please contac t your st sales rappresentative to get the list of orderable commercial part number. memory conditioning core family y=tray r = tape and reel x = tape and reel 90 a=5v, 64mhz b = 3,3 v, 64 mhz a = ?airbag? feature set f = ?full feature? set e = data flash memory b = ?40 to 105 c c = ?40 to 125 c l5 = lqfp144 l3 = lqfp100 60 = 1 mb 54 = 768 kb p = spc56xp54/60 family a = dual core e200z0h 0 = single core e200z0h spc56 = power architecture in 90nm temperature package custom vers. spc56 60 y ap c l3 efa example code: product identifier
revision history spc56xp54x, spc56xp60x 102/104 doc id 18340 rev 3 6 revision history ta bl e 4 4 summarizes revisions to this document. table 44. document revision history date revision substantive changes 21-dec-2010 1 initial release 18-oct-2011 2 in the feature list: revised the first bullet. changed ?up to 82 gpio? to ?up to 80 gpio? changed ?and 82 gpio? to ?and 49 gpio? changed ?flexray module? to ?1 flexray? module?. added section 1.5, feature details table 4: spc56xp54/60 series block summary , added flexray entry. in the ?lqfp176 pinout (top view)? figure: ? pin 104 now is tdi, was pb[5] ? pin 107 now is tdo, was pb[4] ? pin 71 now is nc, was okout ? pin 72 now is nc, was okout_b ? pin 87 now is nc, was nbypass_hv ? pin 88 now is nc, was ipp_livi_b_vddio table 7: pin muxing : pb[6] was clk_out_div5, is now clk_out_div256 removed pb[4] and pb[5] rows in the a[3] row, changed abs[2] to abs[1] section 3.11, dc electrical characteristics , added ?peripherals supply current (5 v and 3.3 v)? table table 14: emi testing specifications , removed all references to sae replaced both table 12: thermal characteristics for 144-pin lqfp and table 13: thermal characteristics for 100-pin lqfp table 30: pllmrfm electrical specifications (v ddpll = 1.08 v to 1.32 v, v ss = v sspll = 0 v, ta = tl to th) , changed the max value of f sys from 120 to 64 table 33: program and erase specifications : removed all tbc changed the initial max value of t bkprg (code flash) from 3.3 to 6.6 s changed the max value of t bkprg (data flash) from 1.9 to 4.1 s changed the max value of t wprogram (data flash) from 300 to 500 s added t esrt row table 17: voltage regulator electrical characteristics , updated v dd_lv_regcor values updated table 18: low voltage monitor electrical characteristics updated table 21: supply current (5.0 v, nvusro[pad3v5v]=0) and table 23: supply current (3.3 v, nvusro[pad3v5v]=1) removed ?nvusro[oscillator_m argin] field description? section. removed ordarable parts tables.
spc56xp54x, spc56xp60x revision history doc id 18340 rev 3 103/104 15-may-2012 3 removed ?enhanced full-featured? version. in the cover page, added ?(1 master/slave, 1 master only)? at the end of the bullet ?2 linflex modules (lin 2.1)? table 2: spc56xp54/60 device comparison , updated the value of ?linflex module? to ?2 (1 master/slave, 1 master only)? section 1.5.4: on-chip flash memory with ecc replaced two occurrences of ?3 wait states? to ?2 wait states? replaced 60 mhz to 64 mhz section 1.5.21: serial communication interface module (linflex) , updated first bullet to ?supports lin master mode (on both modules), lin slave mode (on one module) and uart mode? section 1.5.24: analog-to-digital converter (adc) , removed bullet concerning the analog watchdogs from normal mode features. table 5: supply pins , removed v reg_bypass row. table 6: system pins : added v reg_bypass row added a footnote about reset table 9: absolute maximum ratings : changed typical value of tv dd to 0.25 and added a footnote added v inan entry updated section 3.8.1: voltage regulator electrical characteristics updated table 14: emi testing specifications table 18: low voltage monitor electrical characteristics , changed maximum value of v mlvddok_h to 1.15 table 20: dc electrical characteristics (5.0 v, nvusro[pad3v5v]=0) , added ipu and ipd rows for reset pin. table 21: supply current (5.0 v, nvusro[pad3v5v]=0) : added maximum values of i dd_lv_core for: run, halt, and stop mode updated values and parameter classification of i dd_flash table 22: dc electrical characteristics (3.3 v, nvusro[pad3v5v]=1) , added ipu and ipd rows for reset pin. table 23: supply current (3.3 v, nvusro[pad3v5v]=1) : added maximum values of i dd_lv_core for: run, halt, and stop mode updated values and parameter classification of i dd_flash added table 26: i/o consumption table 31: 16 mhz rc oscillator electrical characteristics , changed minimum and maximum values of ? rcmvar respectively to -6 and 6. renamed figure 16: input equivalent circuit (precise channels) (was ?input equivalent circuit?) added figure 17: input equivalent circuit (extended channels) section 3.15.1: input impedance and adc accuracy , updated equation 4 and equation 10 table 32: adc conversion characteristics , added v inan , c p3 and r sw2 rows table 44. document revision history (continued) date revision substantive changes
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